[PATCH 1/3] x86/APX: support extended SETcc form

[Cui, Lili]

> As indicated during review, spelling/readability-wise
> 
> 	setz	%eax
> 
> is easier than
> 
> 	setzuz	%al
> 
> _and_ properly specifies the full register that's being modified. Permit that form
> to be used, even if the spec writers are unwilling to formally mention it.
> 
> While there also correct the non-ZU EVEX form: That ought to also permit
> memory operands.
> ---
> In principle SETZUcc ought to also permit for memory operands, for (as per the
> spec) EVEX.ZU simply being ignored in that case. However, such forms are rather
> meaningless, so I'm not convinced we really want to permit that.
> 
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
> @@ -42,6 +42,9 @@ Disassembly of section .text:
>  \s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ 	]+setzug r25b
>  \s*[a-f0-9]+:\s*d5 91 9f c1[ 	]+setg   r25b
>  \s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ 	]+\{evex\} setg al
> +\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ 	]+\{evex\} setg (BYTE PTR )?\[rax\]
> +\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ 	]+setzup al
> +\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ 	]+setzunp al
>  \s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ 	]+imulzu ax,bx,0xa
>  \s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ 	]+imulzu ax,WORD PTR \[eax\],0xa
>  \s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ 	]+imulzu r16w,r17w,0xa
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu.d
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu.d
> @@ -42,6 +42,9 @@ Disassembly of section .text:
>  \s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ 	]+setzug %r25b
>  \s*[a-f0-9]+:\s*d5 91 9f c1[ 	]+setg   %r25b
>  \s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ 	]+\{evex\} setg %al
> +\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ 	]+\{evex\} setg \(%rax\)
> +\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ 	]+setzup %al
> +\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ 	]+setzunp %al
>  \s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ 	]+imulzu \$0xa,%bx,%ax
>  \s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ 	]+imulzu \$0xa,\(%eax\),%ax
>  \s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ 	]+imulzu \$0xa,%r17w,%r16w
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu.s
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu.s
> @@ -36,6 +36,9 @@ _start:
>  	setzug   %r25b
>  	setg     %r25b
>  	{evex} setg  %al
> +	{evex} setg  (%rax)
> +	setpe    %eax
> +	setpo    %rax
> 
>  	.intel_syntax noprefix
>  	imulzu ax,bx, 10
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -533,8 +533,11 @@ loopne, 0xe0, x64, JumpByte|No_bSuf|No_w
> 
>  // Set byte on flag instructions.
>  set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
> { Reg8|Unspecified|BaseIndex } -set<cc>, 0xf24<cc:opc>/0, APX_F,
> Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, { Reg8 }
> +set<cc>, 0xf24<cc:opc>/0, APX_F,
> +Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, {
> +Reg8|Unspecified|BaseIndex }
>  setzu<cc>, 0xf24<cc:opc>/0, APX_F,
> Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4|ZU, { Reg8 }
> +// As an extension, allow SETcc without the ZU infix, instead taking
> +the full // register as operand.
> +set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|ZU, {
> +Reg32|Reg64 }
> 
>  // String manipulation.
>  cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}

Thanks for fixing the memory issue with non-ZU EVEX formats, this patch is OK for me.

Lili.