[PATCH v2 4/7][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.

[srinath]

Hi,

This patch fixes encoding and syntax for sve2p1 instructions as mentioned below,
for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html

1) ld1q and st1q first register operand to accept enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions to accept wrapping
   sequence of vector registers.
3) Fixes the encoding for bits 13 and 14 for ld2q's scalar plus scalar encoding.
4) ld3q/st3q and ld4q/st4q scalar plus immediate forms accepts multiple of 3 and 4
respectively.

For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.

I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  #0, MUL VL]  //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0,  #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0,  #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30,  #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30,  #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3,  #-2, MUL VL] // random encoding.

For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than two registers in the list, and the register
numbers are monotonically increasing in increments of one.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.
---
 gas/config/tc-aarch64.c                      |   3 -
 gas/testsuite/gas/aarch64/sme-5-illegal.l    |   8 +-
 gas/testsuite/gas/aarch64/sme-6-illegal.l    |   8 +-
 gas/testsuite/gas/aarch64/sve2p1-1-bad.l     |  14 --
 gas/testsuite/gas/aarch64/sve2p1-1.d         |  14 --
 gas/testsuite/gas/aarch64/sve2p1-1.s         |  15 --
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d |   3 +
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l | 116 +++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s | 119 +++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-4.d         | 144 ++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-4.s         | 147 +++++++++++++++++++
 include/opcode/aarch64.h                     |   3 -
 opcodes/aarch64-opc.c                        |  11 +-
 opcodes/aarch64-tbl.h                        |  43 +++---
 14 files changed, 556 insertions(+), 92 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.s

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