[PATCH v2 3/6] aarch64: Add FP8 Neon and SVE multiplication instructions
Andrew Carlotti
andrew.carlotti@arm.com
Fri Jun 21 18:31:34 GMT 2024
This includes all the instructions under the following features:
- FEAT_FP8FMA (+fp8fma)
- FEAT_FP8DOT4 (+fp8dot4)
- FEAT_FP8DOT2 (+fp8dot2)
- FEAT_SSVE_FP8FMA (+ssve-fp8fma)
- FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
- FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 473097d701f249f4f27df017f0481b858555b5f3..db7741f5915349295e0285e1695b9016779f776a 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -820,6 +820,10 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
{
+ /* Special case S_2B. */
+ if (vectype->type == NT_b && vectype->width == 2)
+ return AARCH64_OPND_QLF_S_2B;
+
/* Special case S_4B. */
if (vectype->type == NT_b && vectype->width == 4)
return AARCH64_OPND_QLF_S_4B;
@@ -1010,7 +1014,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
succeeds; otherwise return FALSE.
Accept only one occurrence of:
- 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
+ 2b 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bool
parse_vector_type_for_operand (aarch64_reg_type reg_type,
@@ -1074,6 +1078,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
if (width != 0 && width * element_size != 64
&& width * element_size != 128
&& !(width == 2 && element_size == 16)
+ && !(width == 2 && element_size == 8)
&& !(width == 4 && element_size == 8))
{
first_error_fmt (_
@@ -6272,6 +6277,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
+ case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
operand->reglane.regno = default_value;
break;
@@ -6793,6 +6799,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
+ case AARCH64_OPND_SVE_Zm3_10_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
@@ -6818,6 +6825,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
+ case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_V;
vector_reg_index:
@@ -10597,6 +10605,15 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)},
{"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)},
{"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES},
+ {"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)},
+ {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)},
+ {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)},
+ {"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA),
+ AARCH64_FEATURES (2, FP8, SME2)},
+ {"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4),
+ AARCH64_FEATURE (SSVE_FP8FMA)},
+ {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
+ AARCH64_FEATURE (SSVE_FP8DOT4)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -10609,7 +10626,12 @@ struct aarch64_virtual_dependency_table
};
static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
- {AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}
+ {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
+ {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)},
+ {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
};
static aarch64_feature_set
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index b29da1f0e8f5ae9be9589ce098674a1c6fb0164f..530d712f55a7e0fc985b7ab04d2dadc18298d189 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -197,6 +197,12 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{fp8} @tab
@tab Enable the Floating Point 8 (FP8) extension.
+@item @code{fp8dot2} @tab @code{fp8dot4}
+ @tab Enable the FP8 2-way dot product instructions.
+@item @code{fp8dot4} @tab @code{fp8fma}
+ @tab Enable the FP8 4-way dot product instructions.
+@item @code{fp8fma} @tab @code{fp8}
+ @tab Enable the FP8 FMA instructions.
@item @code{fp16fml} @tab @code{fp16}
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@@ -275,6 +281,12 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.1.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
+@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4}
+ @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}.
+@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma}
+ @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}.
+@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
@item @code{sve2} @tab @code{sve}
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
new file mode 100644
index 0000000000000000000000000000000000000000..1dac59a5d820670e94f65d7dba510b011609d631
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+fp8dot2
+#error_output: fp8-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l
new file mode 100644
index 0000000000000000000000000000000000000000..155c24b035ccbf664cb2f26bce9f267d4d197931
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l
@@ -0,0 +1,24 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.4h,v0\.8b,v16\.2b\[0\]'
+[^:]*:2: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.4h,v0\.8b,v0\.2b\[8\]'
+[^:]*:3: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.8h,v0\.16b,v16\.2b\[0\]'
+[^:]*:4: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.8h,v0\.16b,v0\.2b\[8\]'
+[^:]*:6: Error: operand mismatch -- `fmlalb v0\.4h,v0\.8b,v0\.8b'
+[^:]*:6: Info: did you mean this\?
+[^:]*:6: Info: \tfmlalb v0\.8h, v0\.16b, v0\.16b
+[^:]*:8: Error: register number out of range 0 to 7 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v8\.b\[0\]'
+[^:]*:9: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v0\.b\[16\]'
+[^:]*:10: Error: register number out of range 0 to 7 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v8\.b\[0\]'
+[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v0\.b\[16\]'
+[^:]*:13: Error: operand mismatch -- `fmlallbb v0\.2s,v0\.8b,v0\.8b'
+[^:]*:13: Info: did you mean this\?
+[^:]*:13: Info: \tfmlallbb v0\.4s, v0\.16b, v0\.16b
+[^:]*:15: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:16: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:17: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:18: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:19: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:21: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:22: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v0\.b\[16\]'
+
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s
new file mode 100644
index 0000000000000000000000000000000000000000..1b75cb68a1dde911285d4d978e6180a61660c5a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s
@@ -0,0 +1,24 @@
+fdot v0.4h, v0.8b, v16.2b[0]
+fdot v0.4h, v0.8b, v0.2b[8]
+fdot v0.8h, v0.16b, v16.2b[0]
+fdot v0.8h, v0.16b, v0.2b[8]
+
+fmlalb v0.4h, v0.8b, v0.8b
+
+fmlalb v0.8h, v0.16b, v8.b[0]
+fmlalb v0.8h, v0.16b, v0.b[16]
+fmlalt v0.8h, v0.16b, v8.b[0]
+fmlalt v0.8h, v0.16b, v0.b[16]
+
+fmlallbb v0.2s, v0.8b, v0.8b
+
+fmlallbb v0.4s, v0.16b, v8.b[0]
+fmlallbb v0.4s, v0.16b, v0.b[16]
+fmlallbt v0.4s, v0.16b, v8.b[0]
+fmlallbt v0.4s, v0.16b, v0.b[16]
+fmlalltb v0.4s, v0.16b, v8.b[0]
+fmlalltb v0.4s, v0.16b, v0.b[16]
+fmlalltt v0.4s, v0.16b, v8.b[0]
+fmlalltt v0.4s, v0.16b, v0.b[16]
+
+
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.d b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d
new file mode 100644
index 0000000000000000000000000000000000000000..7d740b711d2155b7d11638f24cc106da6b3ee109
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d
@@ -0,0 +1,25 @@
+#as: -march=armv8-a+fp8dot2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e40fc00 fdot v0\.4h, v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e5dff77 fdot v23\.4h, v27\.8b, v29\.8b
+ *[0-9a-f]+: 0e53feb9 fdot v25\.4h, v21\.8b, v19\.8b
+ *[0-9a-f]+: 4e40fc00 fdot v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e5dff77 fdot v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e53feb9 fdot v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0f400000 fdot v0\.4h, v0\.8b, v0\.2b\[0\]
+ *[0-9a-f]+: 0f500000 fdot v0\.4h, v0\.8b, v0\.2b\[1\]
+ *[0-9a-f]+: 0f6e0377 fdot v23\.4h, v27\.8b, v14\.2b\[2\]
+ *[0-9a-f]+: 0f4d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[4\]
+ *[0-9a-f]+: 0f7d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[7\]
+ *[0-9a-f]+: 4f400000 fdot v0\.8h, v0\.16b, v0\.2b\[0\]
+ *[0-9a-f]+: 4f500000 fdot v0\.8h, v0\.16b, v0\.2b\[1\]
+ *[0-9a-f]+: 4f6e0377 fdot v23\.8h, v27\.16b, v14\.2b\[2\]
+ *[0-9a-f]+: 4f4d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[4\]
+ *[0-9a-f]+: 4f7d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[7\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.s b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s
new file mode 100644
index 0000000000000000000000000000000000000000..3fff78afbc96bee395523d6e50b66021d207b3f4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s
@@ -0,0 +1,19 @@
+fdot v0.4h, v0.8b, v0.8b
+fdot v23.4h, v27.8b, v29.8b
+fdot v25.4h, v21.8b, v19.8b
+
+fdot v0.8h, v0.16b, v0.16b
+fdot v23.8h, v27.16b, v29.16b
+fdot v25.8h, v21.16b, v19.16b
+
+fdot v0.4h, v0.8b, v0.2b[0]
+fdot v0.4h, v0.8b, v0.2b[1]
+fdot v23.4h, v27.8b, v14.2b[2]
+fdot v25.4h, v21.8b, v13.2b[4]
+fdot v25.4h, v21.8b, v13.2b[7]
+
+fdot v0.8h, v0.16b, v0.2b[0]
+fdot v0.8h, v0.16b, v0.2b[1]
+fdot v23.8h, v27.16b, v14.2b[2]
+fdot v25.8h, v21.16b, v13.2b[4]
+fdot v25.8h, v21.16b, v13.2b[7]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.d b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d
new file mode 100644
index 0000000000000000000000000000000000000000..bf4632c30dddf70b58ca56b8de940c9bd73c8b88
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d
@@ -0,0 +1,21 @@
+#as: -march=armv8-a+fp8dot4
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e00fc00 fdot v0\.2s, v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e1dff77 fdot v23\.2s, v27\.8b, v29\.8b
+ *[0-9a-f]+: 0e13feb9 fdot v25\.2s, v21\.8b, v19\.8b
+ *[0-9a-f]+: 4e00fc00 fdot v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e1dff77 fdot v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e13feb9 fdot v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0f000000 fdot v0\.2s, v0\.8b, v0\.4b\[0\]
+ *[0-9a-f]+: 0f3d0377 fdot v23\.2s, v27\.8b, v29\.4b\[1\]
+ *[0-9a-f]+: 0f330ab9 fdot v25\.2s, v21\.8b, v19\.4b\[3\]
+ *[0-9a-f]+: 4f000000 fdot v0\.4s, v0\.16b, v0\.4b\[0\]
+ *[0-9a-f]+: 4f3d0377 fdot v23\.4s, v27\.16b, v29\.4b\[1\]
+ *[0-9a-f]+: 4f330ab9 fdot v25\.4s, v21\.16b, v19\.4b\[3\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.s b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s
new file mode 100644
index 0000000000000000000000000000000000000000..cfd7283aed6708b5dc5186cb2951969338499ac8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s
@@ -0,0 +1,15 @@
+fdot v0.2s, v0.8b, v0.8b
+fdot v23.2s, v27.8b, v29.8b
+fdot v25.2s, v21.8b, v19.8b
+
+fdot v0.4s, v0.16b, v0.16b
+fdot v23.4s, v27.16b, v29.16b
+fdot v25.4s, v21.16b, v19.16b
+
+fdot v0.2s, v0.8b, v0.4b[0]
+fdot v23.2s, v27.8b, v29.4b[1]
+fdot v25.2s, v21.8b, v19.4b[3]
+
+fdot v0.4s, v0.16b, v0.4b[0]
+fdot v23.4s, v27.16b, v29.4b[1]
+fdot v25.4s, v21.16b, v19.4b[3]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.d b/gas/testsuite/gas/aarch64/fp8-simd-fma.d
new file mode 100644
index 0000000000000000000000000000000000000000..c9c8be6ef1360fcefba802a295123662bc375db2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.d
@@ -0,0 +1,51 @@
+#as: -march=armv8-a+fp8fma
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0ec0fc00 fmlalb v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0eddff77 fmlalb v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0ed3feb9 fmlalb v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4ec0fc00 fmlalt v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4eddff77 fmlalt v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4ed3feb9 fmlalt v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0fc00000 fmlalb v0\.8h, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 0fdd0377 fmlalb v23\.8h, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 0fe702b9 fmlalb v25\.8h, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 0fc70ab9 fmlalb v25\.8h, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 4fc00000 fmlalt v0\.8h, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 4fdd0377 fmlalt v23\.8h, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 4fe702b9 fmlalt v25\.8h, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 4fc70ab9 fmlalt v25\.8h, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 0e00c400 fmlallbb v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0e1dc777 fmlallbb v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0e13c6b9 fmlallbb v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0e40c400 fmlallbt v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0e5dc777 fmlallbt v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0e53c6b9 fmlallbt v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4e00c400 fmlalltb v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e1dc777 fmlalltb v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e13c6b9 fmlalltb v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4e40c400 fmlalltt v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e5dc777 fmlalltt v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e53c6b9 fmlalltt v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 2f008000 fmlallbb v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 2f1d8377 fmlallbb v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 2f2782b9 fmlallbb v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 2f078ab9 fmlallbb v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 2f408000 fmlallbt v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 2f5d8377 fmlallbt v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 2f6782b9 fmlallbt v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 2f478ab9 fmlallbt v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 6f008000 fmlalltb v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 6f1d8377 fmlalltb v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 6f2782b9 fmlalltb v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 6f078ab9 fmlalltb v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 6f408000 fmlalltt v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 6f5d8377 fmlalltt v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 6f6782b9 fmlalltt v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 6f478ab9 fmlalltt v25\.4s, v21\.16b, v7\.b\[8\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.s b/gas/testsuite/gas/aarch64/fp8-simd-fma.s
new file mode 100644
index 0000000000000000000000000000000000000000..be7951465a0e40d1fbe373bfb59fffc3fb0fa74c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.s
@@ -0,0 +1,53 @@
+fmlalb v0.8h, v0.16b, v0.16b
+fmlalb v23.8h, v27.16b, v29.16b
+fmlalb v25.8h, v21.16b, v19.16b
+
+fmlalt v0.8h, v0.16b, v0.16b
+fmlalt v23.8h, v27.16b, v29.16b
+fmlalt v25.8h, v21.16b, v19.16b
+
+fmlalb v0.8h, v0.16b, v0.b[0]
+fmlalb v23.8h, v27.16b, v5.b[3]
+fmlalb v25.8h, v21.16b, v7.b[4]
+fmlalb v25.8h, v21.16b, v7.b[8]
+
+fmlalt v0.8h, v0.16b, v0.b[0]
+fmlalt v23.8h, v27.16b, v5.b[3]
+fmlalt v25.8h, v21.16b, v7.b[4]
+fmlalt v25.8h, v21.16b, v7.b[8]
+
+fmlallbb v0.4s, v0.16b, v0.16b
+fmlallbb v23.4s, v27.16b, v29.16b
+fmlallbb v25.4s, v21.16b, v19.16b
+
+fmlallbt v0.4s, v0.16b, v0.16b
+fmlallbt v23.4s, v27.16b, v29.16b
+fmlallbt v25.4s, v21.16b, v19.16b
+
+fmlalltb v0.4s, v0.16b, v0.16b
+fmlalltb v23.4s, v27.16b, v29.16b
+fmlalltb v25.4s, v21.16b, v19.16b
+
+fmlalltt v0.4s, v0.16b, v0.16b
+fmlalltt v23.4s, v27.16b, v29.16b
+fmlalltt v25.4s, v21.16b, v19.16b
+
+fmlallbb v0.4s, v0.16b, v0.b[0]
+fmlallbb v23.4s, v27.16b, v5.b[3]
+fmlallbb v25.4s, v21.16b, v7.b[4]
+fmlallbb v25.4s, v21.16b, v7.b[8]
+
+fmlallbt v0.4s, v0.16b, v0.b[0]
+fmlallbt v23.4s, v27.16b, v5.b[3]
+fmlallbt v25.4s, v21.16b, v7.b[4]
+fmlallbt v25.4s, v21.16b, v7.b[8]
+
+fmlalltb v0.4s, v0.16b, v0.b[0]
+fmlalltb v23.4s, v27.16b, v5.b[3]
+fmlalltb v25.4s, v21.16b, v7.b[4]
+fmlalltb v25.4s, v21.16b, v7.b[8]
+
+fmlalltt v0.4s, v0.16b, v0.b[0]
+fmlalltt v23.4s, v27.16b, v5.b[3]
+fmlalltt v25.4s, v21.16b, v7.b[4]
+fmlalltt v25.4s, v21.16b, v7.b[8]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.d b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d
new file mode 100644
index 0000000000000000000000000000000000000000..d2633aa84532ba74c27944639a6440e95a2d7c40
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d
@@ -0,0 +1,18 @@
+#as: -march=armv8-a+sve2+fp8dot2
+#as: -march=armv8-a+ssve-fp8dot2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64208400 fdot z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 643d8777 fdot z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 643386b9 fdot z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64204400 fdot z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 642d4f77 fdot z23\.h, z27\.b, z5\.b\[3\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 643f4eb9 fdot z25\.h, z21\.b, z7\.b\[7\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.s b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s
new file mode 100644
index 0000000000000000000000000000000000000000..839222eb7ead5887ee414fc1eba7c0d924241d29
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s
@@ -0,0 +1,9 @@
+fdot z0.h, z0.b, z0.b
+fdot z23.h, z27.b, z29.b
+movprfx z25, z31
+fdot z25.h, z21.b, z19.b
+
+fdot z0.h, z0.b, z0.b[0]
+fdot z23.h, z27.b, z5.b[3]
+movprfx z25, z31
+fdot z25.h, z21.b, z7.b[7]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.d b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d
new file mode 100644
index 0000000000000000000000000000000000000000..ffb8d4ce18b7fcb43b6fe7438c9efa3f1ca68015
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d
@@ -0,0 +1,18 @@
+#as: -march=armv8-a+sve2+fp8dot4
+#as: -march=armv8-a+ssve-fp8dot4
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64608400 fdot z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 647d8777 fdot z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 647386b9 fdot z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64604400 fdot z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 646d4777 fdot z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 647f46b9 fdot z25\.s, z21\.b, z7\.b\[3\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.s b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s
new file mode 100644
index 0000000000000000000000000000000000000000..5cb8227f0403729857bd2fd24281a2d015a8b81b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s
@@ -0,0 +1,9 @@
+fdot z0.s, z0.b, z0.b
+fdot z23.s, z27.b, z29.b
+movprfx z25, z31
+fdot z25.s, z21.b, z19.b
+
+fdot z0.s, z0.b, z0.b[0]
+fdot z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fdot z25.s, z21.b, z7.b[3]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.d b/gas/testsuite/gas/aarch64/fp8-sve-fma.d
new file mode 100644
index 0000000000000000000000000000000000000000..97eae9e8c004e00658fdbdaef89a0261b50cde72
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.d
@@ -0,0 +1,64 @@
+#as: -march=armv8-a+sve2+fp8fma
+#as: -march=armv8-a+ssve-fp8fma
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64a08800 fmlalb z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 64bd8b77 fmlalb z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64b38ab9 fmlalb z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64205000 fmlalb z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64255777 fmlalb z23\.h, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 642f5ab9 fmlalb z25\.h, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 643f5eb9 fmlalb z25\.h, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64208800 fmlallbb z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643d8b77 fmlallbb z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64338ab9 fmlallbb z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 6420c000 fmlallbb z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 6425c777 fmlallbb z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 642fcab9 fmlallbb z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 643fceb9 fmlallbb z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64209800 fmlallbt z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643d9b77 fmlallbt z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64339ab9 fmlallbt z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 6460c000 fmlallbt z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 6465c777 fmlallbt z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 646fcab9 fmlallbt z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 647fceb9 fmlallbt z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 6420a800 fmlalltb z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643dab77 fmlalltb z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 6433aab9 fmlalltb z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64a0c000 fmlalltb z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64a5c777 fmlalltb z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64afcab9 fmlalltb z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64bfceb9 fmlalltb z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 6420b800 fmlalltt z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643dbb77 fmlalltt z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 6433bab9 fmlalltt z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64e0c000 fmlalltt z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64e5c777 fmlalltt z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64efcab9 fmlalltt z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64ffceb9 fmlalltt z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64a09800 fmlalt z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 64bd9b77 fmlalt z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64b39ab9 fmlalt z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64a05000 fmlalt z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64a55777 fmlalt z23\.h, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64af5ab9 fmlalt z25\.h, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64bf5eb9 fmlalt z25\.h, z21\.b, z7\.b\[15\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.s b/gas/testsuite/gas/aarch64/fp8-sve-fma.s
new file mode 100644
index 0000000000000000000000000000000000000000..368e8da3656d755c781c493ab6f886f1edd1621d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.s
@@ -0,0 +1,65 @@
+fmlalb z0.h, z0.b, z0.b
+fmlalb z23.h, z27.b, z29.b
+movprfx z25, z31
+fmlalb z25.h, z21.b, z19.b
+
+fmlalb z0.h, z0.b, z0.b[0]
+fmlalb z23.h, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalb z25.h, z21.b, z7.b[6]
+fmlalb z25.h, z21.b, z7.b[15]
+
+fmlallbb z0.s, z0.b, z0.b
+fmlallbb z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlallbb z25.s, z21.b, z19.b
+
+fmlallbb z0.s, z0.b, z0.b[0]
+fmlallbb z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlallbb z25.s, z21.b, z7.b[6]
+fmlallbb z25.s, z21.b, z7.b[15]
+
+fmlallbt z0.s, z0.b, z0.b
+fmlallbt z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlallbt z25.s, z21.b, z19.b
+
+fmlallbt z0.s, z0.b, z0.b[0]
+fmlallbt z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlallbt z25.s, z21.b, z7.b[6]
+fmlallbt z25.s, z21.b, z7.b[15]
+
+fmlalltb z0.s, z0.b, z0.b
+fmlalltb z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlalltb z25.s, z21.b, z19.b
+
+fmlalltb z0.s, z0.b, z0.b[0]
+fmlalltb z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalltb z25.s, z21.b, z7.b[6]
+fmlalltb z25.s, z21.b, z7.b[15]
+
+fmlalltt z0.s, z0.b, z0.b
+fmlalltt z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlalltt z25.s, z21.b, z19.b
+
+fmlalltt z0.s, z0.b, z0.b[0]
+fmlalltt z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalltt z25.s, z21.b, z7.b[6]
+fmlalltt z25.s, z21.b, z7.b[15]
+
+fmlalt z0.h, z0.b, z0.b
+fmlalt z23.h, z27.b, z29.b
+movprfx z25, z31
+fmlalt z25.h, z21.b, z19.b
+
+fmlalt z0.h, z0.b, z0.b[0]
+fmlalt z23.h, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalt z25.h, z21.b, z7.b[6]
+fmlalt z25.h, z21.b, z7.b[15]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
new file mode 100644
index 0000000000000000000000000000000000000000..f1d98eec161d095e59b922d7e682665634bd8d01
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sve2+fp8dot2
+#error_output: fp8-sve-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l
new file mode 100644
index 0000000000000000000000000000000000000000..4f09c233de0921c415d032b26dc9181d891e791f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l
@@ -0,0 +1,21 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:2: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.b,z0\.b\[4\]'
+[^:]*:4: Error: z0-z7 expected at operand 3 -- `fdot z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:5: Error: register element index out of range 0 to 7 at operand 3 -- `fdot z0\.h,z0\.b,z0\.b\[8\]'
+[^:]*:7: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:8: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb z0\.h,z0\.b,z0\.b\[16\]'
+[^:]*:10: Error: z0-z7 expected at operand 3 -- `fmlallbb z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:13: Error: z0-z7 expected at operand 3 -- `fmlallbt z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:16: Error: z0-z7 expected at operand 3 -- `fmlalltb z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:17: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:19: Error: z0-z7 expected at operand 3 -- `fmlalltt z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:22: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:23: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt z0\.h,z0\.b,z0\.b\[16\]'
+[^:]*:26: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.s,z0\.b,z0\.b\[0\]'
+[^:]*:29: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.h,z0\.b,z0\.b\[0\]'
+[^:]*:32: Warning: predicated instruction expected after `movprfx' -- `fmlalb z25\.h,z0\.b,z0\.b\[0\]'
+[^:]*:35: Warning: predicated instruction expected after `movprfx' -- `fmlallbb z25\.s,z0\.b,z0\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s
new file mode 100644
index 0000000000000000000000000000000000000000..c8e3f9dc84084119984597dbd271fdce4e9bd015
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s
@@ -0,0 +1,35 @@
+fdot z0.s, z0.b, z8.b[0]
+fdot z0.s, z0.b, z0.b[4]
+
+fdot z0.h, z0.b, z8.b[0]
+fdot z0.h, z0.b, z0.b[8]
+
+fmlalb z0.h, z0.b, z8.b[0]
+fmlalb z0.h, z0.b, z0.b[16]
+
+fmlallbb z0.s, z0.b, z8.b[0]
+fmlallbb z0.s, z0.b, z0.b[16]
+
+fmlallbt z0.s, z0.b, z8.b[0]
+fmlallbt z0.s, z0.b, z0.b[16]
+
+fmlalltb z0.s, z0.b, z8.b[0]
+fmlalltb z0.s, z0.b, z0.b[16]
+
+fmlalltt z0.s, z0.b, z8.b[0]
+fmlalltt z0.s, z0.b, z0.b[16]
+
+fmlalt z0.h, z0.b, z8.b[0]
+fmlalt z0.h, z0.b, z0.b[16]
+
+movprfx z25.s, p0/m, z31.s
+fdot z25.s, z0.b, z0.b[0]
+
+movprfx z25.h, p0/z, z31.h
+fdot z25.h, z0.b, z0.b[0]
+
+movprfx z25.h, p0/z, z31.h
+fmlalb z25.h, z0.b, z0.b[0]
+
+movprfx z25.s, p0/m, z31.s
+fmlallbb z25.s, z0.b, z0.b[0]
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 20b7a5e1d4d558aac9632e8213ee58a419f27d68..778c40d87a51cbefe17477185e0e962686ebb114 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -419,11 +419,11 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
@@ -432,11 +432,11 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c83c0a4ebb4e2c129b3363a12fce0608f852f9bf..f2bf994c23651af969f9a37f06144f5e31171519 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -240,6 +240,27 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_LUT,
/* Branch Record Buffer Extension */
AARCH64_FEATURE_BRBE,
+ /* FP8FMA instructions. */
+ AARCH64_FEATURE_FP8FMA,
+ /* FP8DOT4 instructions. */
+ AARCH64_FEATURE_FP8DOT4,
+ /* FP8DOT2 instructions. */
+ AARCH64_FEATURE_FP8DOT2,
+ /* SSVE FP8FMA instructions. */
+ AARCH64_FEATURE_SSVE_FP8FMA,
+ /* SSVE FP8DOT4 instructions. */
+ AARCH64_FEATURE_SSVE_FP8DOT4,
+ /* SSVE FP8DOT2 instructions. */
+ AARCH64_FEATURE_SSVE_FP8DOT2,
+
+ /* Virtual features. These are used to gate instructions that are enabled
+ by either of two (or more) sets of command line flags. */
+ /* +fp8fma+sve or +ssve-fp8fma */
+ AARCH64_FEATURE_FP8FMA_SVE,
+ /* +fp8dot4+sve or +ssve-fp8dot4 */
+ AARCH64_FEATURE_FP8DOT4_SVE,
+ /* +fp8dot2+sve or +ssve-fp8dot2 */
+ AARCH64_FEATURE_FP8DOT2_SVE,
AARCH64_NUM_FEATURES
};
@@ -526,7 +547,9 @@ enum aarch64_opnd
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
- qualifier is S_H. */
+ qualifier is S_H or S_2B. */
+ AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7,
+ used only with qualifier S_B. */
AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */
AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */
AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */
@@ -748,6 +771,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */
AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
+ AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */
AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
@@ -862,11 +886,12 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
- /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
- or 2 x 2 byte are selected by the instruction. Other than that they have
- no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
- for syntactical reasons and is an exception from normal AArch64
- disassembly scheme. */
+ /* These type qualifiers have a special meaning in that they mean 2 x 1 byte,
+ 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that
+ they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are
+ here purely for syntactical reasons and is an exception from normal
+ AArch64 disassembly scheme. */
+ AARCH64_OPND_QLF_S_2B,
AARCH64_OPND_QLF_S_4B,
AARCH64_OPND_QLF_S_2H,
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 5c6a31167c617f59e62a108e00c6e806cd6ec4ed..83d9dd3212751748fbbdc401310bb36d7250f32a 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
{
case AARCH64_OPND_QLF_S_4B:
case AARCH64_OPND_QLF_S_2H:
- /* L:H */
+ /* H:L */
assert (reglane_index < 4);
insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
break;
+ case AARCH64_OPND_QLF_S_2B:
+ /* H:L:M */
+ assert (reglane_index < 8);
+ insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H);
+ break;
default:
return false;
}
@@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
switch (info->qualifier)
{
+ case AARCH64_OPND_QLF_S_B:
+ /* H:imm3 */
+ assert (reglane_index < 16);
+ insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H);
+ break;
case AARCH64_OPND_QLF_S_H:
/* H:L:M */
assert (reglane_index < 8);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 213df616608b3ea3159b4f6b92b65ea319999a0a..7286f178cdc02160559daf8ab797acbc737bd699 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
info->reglane.regno &= 0x1f;
break;
+ case AARCH64_OPND_QLF_S_2B:
+ /* h:l:m */
+ info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
+ FLD_M);
+ info->reglane.regno &= 0xf;
+ break;
default:
return false;
}
@@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
return 0;
switch (info->qualifier)
{
+ case AARCH64_OPND_QLF_S_B:
+ /* H:imm3 */
+ info->reglane.index = extract_fields (code, 0, 2, FLD_H,
+ FLD_imm3_19);
+ info->reglane.regno &= 0x7;
+ break;
+
case AARCH64_OPND_QLF_S_H:
+ case AARCH64_OPND_QLF_S_2B:
if (info->type == AARCH64_OPND_Em16)
{
/* h:l:m */
@@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
}
break;
case AARCH64_OPND_QLF_S_S:
+ case AARCH64_OPND_QLF_S_4B:
/* h:l */
info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
break;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 9b734d63a3b81793d7a7d53afbfec3f1724ee8d7..3136e62375c5b9ce13a4abbf097104af2264b0f9 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -112,6 +112,7 @@ enum aarch64_field_kind
FLD_SVE_i3h3,
FLD_SVE_i3l,
FLD_SVE_i3l2,
+ FLD_SVE_i4l2,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
@@ -169,6 +170,7 @@ enum aarch64_field_kind
FLD_imm3_12,
FLD_imm3_14,
FLD_imm3_15,
+ FLD_imm3_19,
FLD_imm4_0,
FLD_imm4_5,
FLD_imm4_10,
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ea278bfdfe5f78e0bc5173a950386a97fba4cef7..903d3578c2a6822807908ba8a8c53d8de54c96bf 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -308,6 +308,7 @@ const aarch64_field fields[] =
{ 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */
{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
{ 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */
+ { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -365,6 +366,7 @@ const aarch64_field fields[] =
{ 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */
{ 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */
{ 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */
+ { 19, 3 }, /* imm3_19: general immediate in bits [21:19]. */
{ 0, 4 }, /* imm4_0: in rmif instructions. */
{ 5, 4 }, /* imm4_5: in SME instructions. */
{ 10, 4 }, /* imm4_10: in adddg/subg instructions. */
@@ -816,6 +818,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
{4, 1, 0x2, "s", OQK_OPD_VARIANT},
{8, 1, 0x3, "d", OQK_OPD_VARIANT},
{16, 1, 0x4, "q", OQK_OPD_VARIANT},
+ {2, 1, 0x0, "2b", OQK_OPD_VARIANT},
{4, 1, 0x0, "4b", OQK_OPD_VARIANT},
{4, 1, 0x0, "2h", OQK_OPD_VARIANT},
@@ -1814,6 +1817,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
+ case AARCH64_OPND_SVE_Zm3_10_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
size = get_operand_fields_width (get_operand_from_code (type));
@@ -3222,12 +3226,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
01 0:Rm
10 M:Rm
11 RESERVED */
- if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
+ if (type == AARCH64_OPND_Em16
+ && (qualifier == AARCH64_OPND_QLF_S_H
+ || qualifier == AARCH64_OPND_QLF_S_2B)
&& !value_in_range_p (opnd->reglane.regno, 0, 15))
{
set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
return 0;
}
+ if (type == AARCH64_OPND_Em8
+ && !value_in_range_p (opnd->reglane.regno, 0, 7))
+ {
+ set_regno_out_of_range_error (mismatch_detail, idx, 0, 7);
+ return 0;
+ }
break;
case AARCH64_OPND_CLASS_MODIFIED_REG:
@@ -4110,6 +4122,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
+ case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
snprintf (buf, size, "%s[%s]",
style_reg (styler, "v%d.%s", opnd->reglane.regno,
@@ -4235,6 +4248,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_12_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
+ case AARCH64_OPND_SVE_Zm3_10_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index bffb422583a8e27a38d3881716a28cf09ef0c4cd..aae87e1f24a21d58ffb6a0e3667b7764d00ba1f7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2204,6 +2204,10 @@
{ \
QLF3(S_S,S_B,S_B), \
}
+#define OP_SVE_VVV_H_B \
+{ \
+ QLF3(S_H,S_B,S_B), \
+}
#define OP_SVE_VVV_Q_D \
{ \
QLF3(S_Q,S_D,S_D), \
@@ -2453,6 +2457,20 @@
QLF3(V_4S, V_16B, S_4B),\
}
+/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.8B. */
+#define QL_V3DOTH \
+{ \
+ QLF3(V_4H, V_8B, V_8B), \
+ QLF3(V_8H, V_16B, V_16B),\
+}
+
+/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.2B[<index>]. */
+#define QL_V2DOTH \
+{ \
+ QLF3(V_4H, V_8B, S_2B),\
+ QLF3(V_8H, V_16B, S_2B),\
+}
+
/* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D . */
#define QL_SHA512UPT \
{ \
@@ -2519,6 +2537,30 @@
QLF3(V_4S, V_4H, S_H),\
}
+/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.16B. */
+#define QL_V3FML8H \
+{ \
+ QLF3(V_8H, V_16B, V_16B),\
+}
+
+/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.B. */
+#define QL_V2FML8H \
+{ \
+ QLF3(V_8H, V_16B, S_B),\
+}
+
+/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B. */
+#define QL_V3FMLL4S \
+{ \
+ QLF3(V_4S, V_16B, V_16B),\
+}
+
+/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.B. */
+#define QL_V2FMLL4S \
+{ \
+ QLF3(V_4S, V_16B, S_B),\
+}
+
/* e.g. RMIF <Xn>, #<shift>, #<mask>. */
#define QL_RMIF \
{ \
@@ -2752,6 +2794,18 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
AARCH64_FEATURES (2, LUT, SVE2);
static const aarch64_feature_set aarch64_feature_brbe =
AARCH64_FEATURE (BRBE);
+static const aarch64_feature_set aarch64_feature_fp8fma =
+ AARCH64_FEATURE (FP8FMA);
+static const aarch64_feature_set aarch64_feature_fp8dot4 =
+ AARCH64_FEATURE (FP8DOT4);
+static const aarch64_feature_set aarch64_feature_fp8dot2 =
+ AARCH64_FEATURE (FP8DOT2);
+static const aarch64_feature_set aarch64_feature_fp8fma_sve =
+ AARCH64_FEATURES (2, FP8FMA_SVE, SVE);
+static const aarch64_feature_set aarch64_feature_fp8dot4_sve =
+ AARCH64_FEATURES (2, FP8DOT4_SVE, SVE);
+static const aarch64_feature_set aarch64_feature_fp8dot2_sve =
+ AARCH64_FEATURES (2, FP8DOT2_SVE, SVE);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2829,6 +2883,12 @@ static const aarch64_feature_set aarch64_feature_brbe =
#define LUT &aarch64_feature_lut
#define LUT_SVE2 &aarch64_feature_lut_sve2
#define BRBE &aarch64_feature_brbe
+#define FP8FMA &aarch64_feature_fp8fma
+#define FP8DOT4 &aarch64_feature_fp8dot4
+#define FP8DOT2 &aarch64_feature_fp8dot2
+#define FP8FMA_SVE &aarch64_feature_fp8fma_sve
+#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve
+#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3029,6 +3089,18 @@ static const aarch64_feature_set aarch64_feature_brbe =
FLAGS, CONSTRAINTS, 0, NULL }
#define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6615,6 +6687,42 @@ const struct aarch64_opcode aarch64_opcode_table[] =
LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0),
LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0),
+ /* FP8 multiplication AdvSIMD instructions. */
+ FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
+ FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
+ FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ),
+ FP8DOT2_INSN("fdot", 0x0f400000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_V2DOTH, F_SIZEQ),
+ FP8FMA_INSN("fmlalb", 0x0ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0),
+ FP8FMA_INSN("fmlalt", 0x4ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0),
+ FP8FMA_INSN("fmlalb", 0x0fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0),
+ FP8FMA_INSN("fmlalt", 0x4fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0),
+ FP8FMA_INSN("fmlallbb", 0x0e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
+ FP8FMA_INSN("fmlallbt", 0x0e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
+ FP8FMA_INSN("fmlalltb", 0x4e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
+ FP8FMA_INSN("fmlalltt", 0x4e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
+ FP8FMA_INSN("fmlallbb", 0x2f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0),
+ FP8FMA_INSN("fmlallbt", 0x2f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0),
+ FP8FMA_INSN("fmlalltb", 0x6f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0),
+ FP8FMA_INSN("fmlalltt", 0x6f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0),
+
+ /* FP8 multiplication SVE instructions. */
+ FP8DOT4_SVE_INSNC("fdot", 0x64608400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8DOT4_SVE_INSNC("fdot", 0x64604400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8DOT2_SVE_INSNC("fdot", 0x64208400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8DOT2_SVE_INSNC("fdot", 0x64204400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalb", 0x64a08800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalb", 0x64205000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlallbb", 0x64208800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlallbb", 0x6420c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlallbt", 0x64209800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlallbt", 0x6460c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalltb", 0x6420a800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalltb", 0x64a0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalltt", 0x6420b800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalltt", 0x64e0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -6690,6 +6798,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a SIMD vector element") \
Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \
"a SIMD vector element limited to V0-V15") \
+ Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \
+ "a SIMD vector element limited to V0-V7") \
Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \
"a SIMD vector without a type qualifier encoding a bit index") \
Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \
@@ -7113,6 +7223,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
+ Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \
+ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \
+ "an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \
4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \
"an indexed SVE vector register") \
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