[PATCH 0/6] x86: a few more optimizations

[Jan Beulich]

On 17.06.2024 04:51, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, June 14, 2024 8:11 PM
>> To: Binutils <binutils@sourceware.org>
>> Cc: H.J. Lu <hjl.tools@gmail.com>; Cui, Lili <lili.cui@intel.com>
>> Subject: [PATCH 0/6] x86: a few more optimizations
>>
>> APX {nf} insn forms present a number of interesting optimization
>> opportunities, often mostly for size. There are a few more that I'm
>> aware of, but where I'm less convinced that input code would really
>> ever be written like this:
>>
>> 1) Quite a few operations could be converted to plain MOV. For example
>>
>> 	{nf} xor %cl, %cl
>> 	{nf} sub %cl, %cl
>> 	{nf} and $0, %cl
>>
>> can all be replaced by the much shorter
>>
>> 	mov	$0, %cl
>>
>> 2) Certain forms of IMUL{,ZU} with a power-of-2 immediate could be
>> converted to SHL. This could be beneficial even when size doesn't
>> shrink, for SHL still having better latency/throughput.
> 
> I suppose the first optimization is ok whether for compiler to do that or
> assembler to do that. I don't see problems from the first glance since the
> behavior seems the same.
> 
> The imul -> shl optimization should be done in compiler since it is
> latency/throughput related.

Optimizations done in the assembler are, imo, mainly targeting hand-
written assembly. Any optimizations whatsoever in compiled code should
be carried out by the compiler. Hence me having said "would really ever
be written like this" (and specifically not "emitted").

Jan