[committed] RISC-V: Tidy vendor core-v extension gas testcases
Nelson Chu
nelson@rivosinc.com
Wed Jun 5 10:17:28 GMT 2024
1. Combined testcases into one if they use same extention name.
2. Likewise for the fail testcases.
3. Renamed with x-cv prefix, just like what other vendors did.
gas/
* testsuite/gas/riscv/cv-alu-*: Combined and renamed to
x-cv-alu. Likewise for fail testcases, to x-cv-alu-fail*.
* testsuite/gas/riscv/cv-bi-*: Likewise, but renamed to
x-cv-bi and x-cv-bi-fail.
* testsuite/gas/riscv/cv-elw-*: Likewise, but renamed to
x-cv-elw and x-cv-elw-fail.
* testsuite/gas/riscv/cv-mac-*: Likewise, but renamed to
x-cv-mac and x-cv-mac-fail.
* testsuite/gas/riscv/cv-mem-*: Likewise, but renamed to
x-cv-mem and x-cv-mem-fail.
---
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 -
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 -
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 --
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 -
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ---
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ---
.../gas/riscv/cv-alu-fail-operand-01.d | 3 -
.../gas/riscv/cv-alu-fail-operand-01.l | 32 ---
.../gas/riscv/cv-alu-fail-operand-01.s | 33 ---
.../gas/riscv/cv-alu-fail-operand-02.d | 3 -
.../gas/riscv/cv-alu-fail-operand-02.l | 32 ---
.../gas/riscv/cv-alu-fail-operand-02.s | 33 ---
.../gas/riscv/cv-alu-fail-operand-03.d | 3 -
.../gas/riscv/cv-alu-fail-operand-03.l | 25 --
.../gas/riscv/cv-alu-fail-operand-03.s | 26 --
.../gas/riscv/cv-alu-fail-operand-04.d | 3 -
.../gas/riscv/cv-alu-fail-operand-04.l | 3 -
.../gas/riscv/cv-alu-fail-operand-04.s | 4 -
.../gas/riscv/cv-alu-fail-operand-05.d | 3 -
.../gas/riscv/cv-alu-fail-operand-05.l | 9 -
.../gas/riscv/cv-alu-fail-operand-05.s | 10 -
.../gas/riscv/cv-alu-fail-operand-06.d | 3 -
.../gas/riscv/cv-alu-fail-operand-06.l | 9 -
.../gas/riscv/cv-alu-fail-operand-06.s | 10 -
.../gas/riscv/cv-alu-fail-operand-07.d | 3 -
.../gas/riscv/cv-alu-fail-operand-07.l | 33 ---
.../gas/riscv/cv-alu-fail-operand-07.s | 34 ---
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 --------
gas/testsuite/gas/riscv/cv-bi-beqimm.d | 12 -
gas/testsuite/gas/riscv/cv-bi-bneimm.d | 12 -
gas/testsuite/gas/riscv/cv-bi-bneimm.s | 4 -
gas/testsuite/gas/riscv/cv-bi-fail-march.d | 3 -
gas/testsuite/gas/riscv/cv-bi-fail-march.l | 3 -
gas/testsuite/gas/riscv/cv-bi-fail-march.s | 5 -
.../gas/riscv/cv-bi-fail-operand-01.d | 3 -
.../gas/riscv/cv-bi-fail-operand-01.l | 3 -
.../gas/riscv/cv-bi-fail-operand-01.s | 4 -
.../gas/riscv/cv-bi-fail-operand-02.d | 3 -
.../gas/riscv/cv-bi-fail-operand-02.l | 3 -
.../gas/riscv/cv-bi-fail-operand-02.s | 4 -
.../gas/riscv/cv-bi-fail-operand-03.d | 3 -
.../gas/riscv/cv-bi-fail-operand-03.l | 9 -
.../gas/riscv/cv-bi-fail-operand-03.s | 10 -
gas/testsuite/gas/riscv/cv-elw-fail-march.d | 3 -
gas/testsuite/gas/riscv/cv-elw-fail-march.s | 41 ---
gas/testsuite/gas/riscv/cv-elw-fail.d | 3 -
gas/testsuite/gas/riscv/cv-elw-fail.l | 5 -
gas/testsuite/gas/riscv/cv-elw-fail.s | 8 -
gas/testsuite/gas/riscv/cv-elw-pass.d | 46 ----
gas/testsuite/gas/riscv/cv-elw-pass.s | 41 ---
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 -
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 --
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 --
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 -
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 -------
gas/testsuite/gas/riscv/cv-mem-fail-march.d | 3 -
gas/testsuite/gas/riscv/cv-mem-fail-march.l | 25 --
gas/testsuite/gas/riscv/cv-mem-fail-march.s | 26 --
.../gas/riscv/cv-mem-fail-operand-01.d | 3 -
.../gas/riscv/cv-mem-fail-operand-01.l | 21 --
.../gas/riscv/cv-mem-fail-operand-01.s | 22 --
.../gas/riscv/cv-mem-fail-operand-02.d | 3 -
.../gas/riscv/cv-mem-fail-operand-02.l | 13 -
.../gas/riscv/cv-mem-fail-operand-02.s | 14 -
.../gas/riscv/cv-mem-fail-operand-03.d | 3 -
.../gas/riscv/cv-mem-fail-operand-03.l | 33 ---
.../gas/riscv/cv-mem-fail-operand-03.s | 34 ---
.../gas/riscv/cv-mem-fail-operand-04.d | 3 -
.../gas/riscv/cv-mem-fail-operand-04.l | 41 ---
.../gas/riscv/cv-mem-fail-operand-04.s | 42 ---
.../gas/riscv/cv-mem-fail-operand-05.d | 3 -
.../gas/riscv/cv-mem-fail-operand-05.l | 25 --
.../gas/riscv/cv-mem-fail-operand-05.s | 26 --
gas/testsuite/gas/riscv/cv-mem-lbpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lbpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lbrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lbrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lbrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lbrrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lbupost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lbupost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lburr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lburr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lburrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lburrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhrrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhupost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhupost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhurr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhurr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lhurrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lhurrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lwpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lwpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lwrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lwrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-lwrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-lwrrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-sbpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-sbpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-sbrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-sbrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-sbrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-sbrrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-shpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-shpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-shrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-shrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-shrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-shrrpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-swpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-swpost.s | 4 -
gas/testsuite/gas/riscv/cv-mem-swrr.d | 12 -
gas/testsuite/gas/riscv/cv-mem-swrr.s | 4 -
gas/testsuite/gas/riscv/cv-mem-swrrpost.d | 12 -
gas/testsuite/gas/riscv/cv-mem-swrrpost.s | 4 -
gas/testsuite/gas/riscv/x-cv-alu-fail.d | 2 +
gas/testsuite/gas/riscv/x-cv-alu-fail.l | 243 ++++++++++++++++++
gas/testsuite/gas/riscv/x-cv-alu-fail.s | 170 ++++++++++++
gas/testsuite/gas/riscv/x-cv-alu.d | 102 ++++++++
.../gas/riscv/{cv-alu-insns.s => x-cv-alu.s} | 1 -
gas/testsuite/gas/riscv/x-cv-bi-fail.d | 2 +
gas/testsuite/gas/riscv/x-cv-bi-fail.l | 19 ++
gas/testsuite/gas/riscv/x-cv-bi-fail.s | 24 ++
gas/testsuite/gas/riscv/x-cv-bi.d | 15 ++
.../gas/riscv/{cv-bi-beqimm.s => x-cv-bi.s} | 3 +
gas/testsuite/gas/riscv/x-cv-elw-fail.d | 2 +
.../{cv-elw-fail-march.l => x-cv-elw-fail.l} | 4 +
gas/testsuite/gas/riscv/x-cv-elw-fail.s | 13 +
gas/testsuite/gas/riscv/x-cv-elw.d | 45 ++++
gas/testsuite/gas/riscv/x-cv-elw.s | 40 +++
gas/testsuite/gas/riscv/x-cv-mac-fail.d | 2 +
...{cv-mac-fail-operand.l => x-cv-mac-fail.l} | 78 ++++++
...{cv-mac-fail-operand.s => x-cv-mac-fail.s} | 17 +-
gas/testsuite/gas/riscv/x-cv-mac.d | 87 +++++++
.../gas/riscv/{cv-mac-insns.s => x-cv-mac.s} | 3 +-
gas/testsuite/gas/riscv/x-cv-mem-fail.d | 2 +
gas/testsuite/gas/riscv/x-cv-mem-fail.l | 201 +++++++++++++++
gas/testsuite/gas/riscv/x-cv-mem-fail.s | 143 +++++++++++
gas/testsuite/gas/riscv/x-cv-mem.d | 81 ++++++
gas/testsuite/gas/riscv/x-cv-mem.s | 103 ++++++++
146 files changed, 1393 insertions(+), 1629 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
delete mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
delete mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d
delete mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.s
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.d
delete mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-alu-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-cv-alu-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-cv-alu-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-alu.d
rename gas/testsuite/gas/riscv/{cv-alu-insns.s => x-cv-alu.s} (99%)
create mode 100644 gas/testsuite/gas/riscv/x-cv-bi-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-cv-bi-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-cv-bi-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-bi.d
rename gas/testsuite/gas/riscv/{cv-bi-beqimm.s => x-cv-bi.s} (51%)
create mode 100644 gas/testsuite/gas/riscv/x-cv-elw-fail.d
rename gas/testsuite/gas/riscv/{cv-elw-fail-march.l => x-cv-elw-fail.l} (93%)
create mode 100644 gas/testsuite/gas/riscv/x-cv-elw-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-elw.d
create mode 100644 gas/testsuite/gas/riscv/x-cv-elw.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-mac-fail.d
rename gas/testsuite/gas/riscv/{cv-mac-fail-operand.l => x-cv-mac-fail.l} (54%)
rename gas/testsuite/gas/riscv/{cv-mac-fail-operand.s => x-cv-mac-fail.s} (91%)
create mode 100644 gas/testsuite/gas/riscv/x-cv-mac.d
rename gas/testsuite/gas/riscv/{cv-mac-insns.s => x-cv-mac.s} (98%)
create mode 100644 gas/testsuite/gas/riscv/x-cv-mem-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-cv-mem-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-cv-mem-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-cv-mem.d
create mode 100644 gas/testsuite/gas/riscv/x-cv-mem.s
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
deleted file mode 100644
index 907b043aebc..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-boundaries.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-boundaries.s
-#error_output: cv-alu-boundaries.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
deleted file mode 100644
index fae4022244c..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-boundaries.l
+++ /dev/null
@@ -1,14 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.subnr 10,t3,t6'
-.*: Error: illegal operands `cv.addrnr t4,26,t6'
-.*: Error: illegal operands `cv.subunr t6,t3,15'
-.*: Error: instruction cv.clipu requires absolute expression
-.*: Error: instruction cv.addn requires absolute expression
-.*: Error: illegal operands `cv.clipu t0,t3,-10'
-.*: Error: illegal operands `cv.clipu t0,t3,500'
-.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
-.*: Error: illegal operands `cv.addn t0,t3,t6,302'
-.*: Error: illegal operands `cv.clipu t0,t3,-1'
-.*: Error: illegal operands `cv.clipu t0,t3,32'
-.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
-.*: Error: illegal operands `cv.addn t0,t3,t6,32'
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
deleted file mode 100644
index bb4da949b4a..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-boundaries.s
+++ /dev/null
@@ -1,27 +0,0 @@
-# Destination must be of type register
-target:
- cv.subnr 10, t3, t6
-# Source 1 must be of type register
- cv.addrnr t4, 26, t6
-# Source 2 must be of type register
- cv.subunr t6, t3, 15
-# Five bit immediate must be an absolute value
- cv.clipu t0, t3, t6
-# Five bit immediate must be an absolute value
- cv.addn t0, t3, t6, t2
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.clipu t0, t3, -10
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.clipu t0, t3, 500
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.addn t0, t3, t6, -60
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.addn t0, t3, t6, 302
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.clipu t0, t3, -1
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.clipu t0, t3, 32
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.addn t0, t3, t6, -1
-# Five bit immediate must be an absolute value in range [0, 31]
- cv.addn t0, t3, t6, 32
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
deleted file mode 100644
index 963aa4012da..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-march.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i
-#source: cv-alu-fail-march.s
-#error_output: cv-alu-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
deleted file mode 100644
index 11e5a7cd279..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-march.l
+++ /dev/null
@@ -1,32 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' required
-.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' required
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
deleted file mode 100644
index 8dd39b7301f..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-march.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Absence of xcv or xcvalu march option disables all CORE-V general ALU ops extensions
-target:
- cv.abs t4,t2
- cv.slet t4,t2,t6
- cv.sletu t4,t2,t6
- cv.min t4,t2,t6
- cv.minu t4,t2,t6
- cv.max t4,t2,t6
- cv.maxu t4,t2,t6
- cv.exths t4,t2
- cv.exthz t4,t2
- cv.extbs t4,t2
- cv.extbz t4,t2
- cv.clip t4,t2,5
- cv.clipu t4,t2,5
- cv.clipr t4,t2,t6
- cv.clipur t4,t2,t6
- cv.addn t4, t2, t0, 4
- cv.addun t4, t2, t0, 4
- cv.addrn t6, t0, t3, 9
- cv.addurn t6, t0, t3, 14
- cv.addnr t6, t0, t3
- cv.addunr t6, t0, t3
- cv.addrnr t6, t0, t3
- cv.addurnr t6, t0, t3
- cv.subn t6, t0, t3, 6
- cv.subun t6, t0, t3, 24
- cv.subrn t6, t0, t3, 21
- cv.suburn t6, t0, t3, 3
- cv.subnr t6, t0, t3
- cv.subunr t6, t0, t3
- cv.subrnr t6, t0, t3
- cv.suburnr t6, t0, t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
deleted file mode 100644
index 81b17348c32..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-01.s
-#error_output: cv-alu-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
deleted file mode 100644
index f670e4341fa..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
+++ /dev/null
@@ -1,32 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.abs 5,t2'
-.*: Error: illegal operands `cv.slet 10,t2,t6'
-.*: Error: illegal operands `cv.sletu 11,t2,t6'
-.*: Error: illegal operands `cv.min 15,t2,t6'
-.*: Error: illegal operands `cv.minu 16,t2,t6'
-.*: Error: illegal operands `cv.max 8,t2,t6'
-.*: Error: illegal operands `cv.maxu 3,t2,t6'
-.*: Error: illegal operands `cv.exths 2,t2'
-.*: Error: illegal operands `cv.exthz 6,t2'
-.*: Error: illegal operands `cv.extbs 4,t2'
-.*: Error: illegal operands `cv.extbz 7,t2'
-.*: Error: illegal operands `cv.clip 17,t2,5'
-.*: Error: illegal operands `cv.clipu 11,t2,5'
-.*: Error: illegal operands `cv.clipr 16,t2,t6'
-.*: Error: illegal operands `cv.clipur 15,t2,t6'
-.*: Error: illegal operands `cv.addn 9,t2,t0,4'
-.*: Error: illegal operands `cv.addun 30,t2,t0,4'
-.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
-.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
-.*: Error: illegal operands `cv.addnr 2,t0,t3'
-.*: Error: illegal operands `cv.addunr 26,t0,t3'
-.*: Error: illegal operands `cv.addrnr 3,t0,t3'
-.*: Error: illegal operands `cv.addurnr 14,t0,t3'
-.*: Error: illegal operands `cv.subn 15,t0,t3,6'
-.*: Error: illegal operands `cv.subun 9,t0,t3,24'
-.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
-.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
-.*: Error: illegal operands `cv.subnr 3,t0,t3'
-.*: Error: illegal operands `cv.subunr 12,t0,t3'
-.*: Error: illegal operands `cv.subrnr 13,t0,t3'
-.*: Error: illegal operands `cv.suburnr 8,t0,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
deleted file mode 100644
index 7920ebd53ec..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Destination must be of type register
-target:
- cv.abs 5,t2
- cv.slet 10,t2,t6
- cv.sletu 11,t2,t6
- cv.min 15,t2,t6
- cv.minu 16,t2,t6
- cv.max 8,t2,t6
- cv.maxu 3,t2,t6
- cv.exths 2,t2
- cv.exthz 6,t2
- cv.extbs 4,t2
- cv.extbz 7,t2
- cv.clip 17,t2,5
- cv.clipu 11,t2,5
- cv.clipr 16,t2,t6
- cv.clipur 15,t2,t6
- cv.addn 9,t2,t0,4
- cv.addun 30,t2,t0,4
- cv.addrn 21,t0,t3,9
- cv.addurn 6,t0,t3,14
- cv.addnr 2,t0,t3
- cv.addunr 26,t0,t3
- cv.addrnr 3,t0,t3
- cv.addurnr 14,t0,t3
- cv.subn 15,t0,t3,6
- cv.subun 9,t0,t3,24
- cv.subrn 24,t0,t3,21
- cv.suburn 25,t0,t3,3
- cv.subnr 3,t0,t3
- cv.subunr 12,t0,t3
- cv.subrnr 13,t0,t3
- cv.suburnr 8,t0,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
deleted file mode 100644
index 46645aaf864..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-02.s
-#error_output: cv-alu-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
deleted file mode 100644
index 0a888c7251b..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
+++ /dev/null
@@ -1,32 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.abs t4,5'
-.*: Error: illegal operands `cv.slet t4,7,t6'
-.*: Error: illegal operands `cv.sletu t4,3,t6'
-.*: Error: illegal operands `cv.min t4,5,t6'
-.*: Error: illegal operands `cv.minu t4,3,t6'
-.*: Error: illegal operands `cv.max t4,4,t6'
-.*: Error: illegal operands `cv.maxu t4,6,t6'
-.*: Error: illegal operands `cv.exths t4,30'
-.*: Error: illegal operands `cv.exthz t4,23'
-.*: Error: illegal operands `cv.extbs t4,25'
-.*: Error: illegal operands `cv.extbz t4,21'
-.*: Error: illegal operands `cv.clip t4,2,5'
-.*: Error: illegal operands `cv.clipu t4,16,5'
-.*: Error: illegal operands `cv.clipr t4,17,t6'
-.*: Error: illegal operands `cv.clipur t4,14,t6'
-.*: Error: illegal operands `cv.addn t4,5,t0,4'
-.*: Error: illegal operands `cv.addun t4,18,t0,4'
-.*: Error: illegal operands `cv.addrn t6,19,t3,9'
-.*: Error: illegal operands `cv.addurn t6,4,t3,14'
-.*: Error: illegal operands `cv.addnr t6,6,t3'
-.*: Error: illegal operands `cv.addunr t6,7,t3'
-.*: Error: illegal operands `cv.addrnr t6,9,t3'
-.*: Error: illegal operands `cv.addurnr t6,5,t3'
-.*: Error: illegal operands `cv.subn t6,11,t3,6'
-.*: Error: illegal operands `cv.subun t6,14,t3,24'
-.*: Error: illegal operands `cv.subrn t6,15,t3,21'
-.*: Error: illegal operands `cv.suburn t6,24,t3,3'
-.*: Error: illegal operands `cv.subnr t6,4,t3'
-.*: Error: illegal operands `cv.subunr t6,8,t3'
-.*: Error: illegal operands `cv.subrnr t6,7,t3'
-.*: Error: illegal operands `cv.suburnr t6,6,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
deleted file mode 100644
index 6083f1f5044..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Source 1 must be of type register
-target:
- cv.abs t4,5
- cv.slet t4,7,t6
- cv.sletu t4,3,t6
- cv.min t4,5,t6
- cv.minu t4,3,t6
- cv.max t4,4,t6
- cv.maxu t4,6,t6
- cv.exths t4,30
- cv.exthz t4,23
- cv.extbs t4,25
- cv.extbz t4,21
- cv.clip t4,2,5
- cv.clipu t4,16,5
- cv.clipr t4,17,t6
- cv.clipur t4,14,t6
- cv.addn t4,5,t0,4
- cv.addun t4,18,t0,4
- cv.addrn t6,19,t3,9
- cv.addurn t6,4,t3,14
- cv.addnr t6,6,t3
- cv.addunr t6,7,t3
- cv.addrnr t6,9,t3
- cv.addurnr t6,5,t3
- cv.subn t6,11,t3,6
- cv.subun t6,14,t3,24
- cv.subrn t6,15,t3,21
- cv.suburn t6,24,t3,3
- cv.subnr t6,4,t3
- cv.subunr t6,8,t3
- cv.subrnr t6,7,t3
- cv.suburnr t6,6,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
deleted file mode 100644
index 6f681289d12..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-03.s
-#error_output: cv-alu-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
deleted file mode 100644
index c7a11184996..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
+++ /dev/null
@@ -1,25 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.slet t4,t2,3'
-.*: Error: illegal operands `cv.sletu t4,t2,4'
-.*: Error: illegal operands `cv.min t4,t2,13'
-.*: Error: illegal operands `cv.minu t4,t2,7'
-.*: Error: illegal operands `cv.max t4,t2,17'
-.*: Error: illegal operands `cv.maxu t4,t2,30'
-.*: Error: illegal operands `cv.clipr t4,t2,18'
-.*: Error: illegal operands `cv.clipur t4,t2,29'
-.*: Error: illegal operands `cv.addn t4,t2,24,4'
-.*: Error: illegal operands `cv.addun t4,t2,6,4'
-.*: Error: illegal operands `cv.addrn t6,t0,7,9'
-.*: Error: illegal operands `cv.addurn t6,t0,18,14'
-.*: Error: illegal operands `cv.addnr t6,t0,15'
-.*: Error: illegal operands `cv.addunr t6,t0,24'
-.*: Error: illegal operands `cv.addrnr t6,t0,3'
-.*: Error: illegal operands `cv.addurnr t6,t0,2'
-.*: Error: illegal operands `cv.subn t6,t0,1,6'
-.*: Error: illegal operands `cv.subun t6,t0,8,24'
-.*: Error: illegal operands `cv.subrn t6,t0,18,21'
-.*: Error: illegal operands `cv.suburn t6,t0,25,3'
-.*: Error: illegal operands `cv.subnr t6,t0,14'
-.*: Error: illegal operands `cv.subunr t6,t0,7'
-.*: Error: illegal operands `cv.subrnr t6,t0,18'
-.*: Error: illegal operands `cv.suburnr t6,t0,26'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
deleted file mode 100644
index 64ee8703579..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
+++ /dev/null
@@ -1,26 +0,0 @@
-# Source 2 must be of type register
-target:
- cv.slet t4,t2,3
- cv.sletu t4,t2,4
- cv.min t4,t2,13
- cv.minu t4,t2,7
- cv.max t4,t2,17
- cv.maxu t4,t2,30
- cv.clipr t4,t2,18
- cv.clipur t4,t2,29
- cv.addn t4,t2,24,4
- cv.addun t4,t2,6,4
- cv.addrn t6,t0,7,9
- cv.addurn t6,t0,18,14
- cv.addnr t6,t0,15
- cv.addunr t6,t0,24
- cv.addrnr t6,t0,3
- cv.addurnr t6,t0,2
- cv.subn t6,t0,1,6
- cv.subun t6,t0,8,24
- cv.subrn t6,t0,18,21
- cv.suburn t6,t0,25,3
- cv.subnr t6,t0,14
- cv.subunr t6,t0,7
- cv.subrnr t6,t0,18
- cv.suburnr t6,t0,26
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
deleted file mode 100644
index 634d9bfe091..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-04.s
-#error_output: cv-alu-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
deleted file mode 100644
index d6fd960f9e0..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*: Error: instruction cv.clip requires absolute expression
-.*: Error: instruction cv.clipu requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
deleted file mode 100644
index b97d52a77ab..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
+++ /dev/null
@@ -1,4 +0,0 @@
-# Five bit immediate must be an absolute value
-target:
- cv.clip t4,t2,t3
- cv.clipu t4,t2,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
deleted file mode 100644
index 1b90d3e5757..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-05.s
-#error_output: cv-alu-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
deleted file mode 100644
index 05b5289e743..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
+++ /dev/null
@@ -1,9 +0,0 @@
-.*: Assembler messages:
-.*: Error: instruction cv.addn requires absolute expression
-.*: Error: instruction cv.addun requires absolute expression
-.*: Error: instruction cv.addrn requires absolute expression
-.*: Error: instruction cv.addurn requires absolute expression
-.*: Error: instruction cv.subn requires absolute expression
-.*: Error: instruction cv.subun requires absolute expression
-.*: Error: instruction cv.subrn requires absolute expression
-.*: Error: instruction cv.suburn requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
deleted file mode 100644
index 1b0ac6f2d59..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# Five bit immediate must be an absolute value
-target:
- cv.addn t4,t2,t0,t3
- cv.addun t4,t2,t0,t3
- cv.addrn t6,t0,t3,t2
- cv.addurn t6,t0,t3,t2
- cv.subn t6,t0,t3,t2
- cv.subun t6,t0,t3,t2
- cv.subrn t6,t0,t3,t2
- cv.suburn t6,t0,t3,t2
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
deleted file mode 100644
index 0a49e682c85..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-06.s
-#error_output: cv-alu-fail-operand-06.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
deleted file mode 100644
index d8059cb5e3a..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
+++ /dev/null
@@ -1,9 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.clip t0,t3,-1'
-.*: Error: illegal operands `cv.clipu t0,t3,-1'
-.*: Error: illegal operands `cv.clip t0,t3,-400'
-.*: Error: illegal operands `cv.clipu t0,t3,-985'
-.*: Error: illegal operands `cv.clip t0,t3,32'
-.*: Error: illegal operands `cv.clipu t0,t3,32'
-.*: Error: illegal operands `cv.clip t0,t3,859'
-.*: Error: illegal operands `cv.clipu t0,t3,7283'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
deleted file mode 100644
index 1b810bdda55..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# Five bit immediate must be an absolute value in range [0, 31]
-target:
- cv.clip t0,t3,-1
- cv.clipu t0,t3,-1
- cv.clip t0,t3,-400
- cv.clipu t0,t3,-985
- cv.clip t0,t3,32
- cv.clipu t0,t3,32
- cv.clip t0,t3,859
- cv.clipu t0,t3,7283
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
deleted file mode 100644
index 06d17fede7c..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvalu
-#source: cv-alu-fail-operand-07.s
-#error_output: cv-alu-fail-operand-07.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
deleted file mode 100644
index 5a34156afc3..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
+++ /dev/null
@@ -1,33 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
-.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
-.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
-.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
-.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
-.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
-.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
-.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
-.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
-.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
-.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
-.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
-.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
-.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
-.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
-.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
-.*: Error: illegal operands `cv.addn t4,t2,t0,32'
-.*: Error: illegal operands `cv.addun t4,t2,t0,32'
-.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
-.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
-.*: Error: illegal operands `cv.subn t6,t0,t3,32'
-.*: Error: illegal operands `cv.subun t6,t0,t3,32'
-.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
-.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
-.*: Error: illegal operands `cv.addn t4,t2,t0,320'
-.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
-.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
-.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
-.*: Error: illegal operands `cv.subn t6,t0,t3,89'
-.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
-.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
-.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
deleted file mode 100644
index 04788f69ddd..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
+++ /dev/null
@@ -1,34 +0,0 @@
-# Five bit immediate must be an absolute value in range [0, 31]
-target:
- cv.addn t4,t2,t0,-1
- cv.addun t4,t2,t0,-1
- cv.addrn t6,t0,t3,-1
- cv.addurn t6,t0,t3,-1
- cv.subn t6,t0,t3,-1
- cv.subun t6,t0,t3,-1
- cv.subrn t6,t0,t3,-1
- cv.suburn t6,t0,t3,-1
- cv.addn t4,t2,t0,-34
- cv.addun t4,t2,t0,-3556
- cv.addrn t6,t0,t3,-212
- cv.addurn t6,t0,t3,-6584
- cv.subn t6,t0,t3,-89
- cv.subun t6,t0,t3,-9034
- cv.subrn t6,t0,t3,-234
- cv.suburn t6,t0,t3,-284
- cv.addn t4,t2,t0,32
- cv.addun t4,t2,t0,32
- cv.addrn t6,t0,t3,32
- cv.addurn t6,t0,t3,32
- cv.subn t6,t0,t3,32
- cv.subun t6,t0,t3,32
- cv.subrn t6,t0,t3,32
- cv.suburn t6,t0,t3,32
- cv.addn t4,t2,t0,320
- cv.addun t4,t2,t0,34534
- cv.addrn t6,t0,t3,254
- cv.addurn t6,t0,t3,398
- cv.subn t6,t0,t3,89
- cv.subun t6,t0,t3,3489
- cv.subrn t6,t0,t3,143
- cv.suburn t6,t0,t3,234
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d b/gas/testsuite/gas/riscv/cv-alu-insns.d
deleted file mode 100644
index 784cf5ca6cb..00000000000
--- a/gas/testsuite/gas/riscv/cv-alu-insns.d
+++ /dev/null
@@ -1,102 +0,0 @@
-#as: -march=rv32i_xcvalu
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
-[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
-[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
-[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
-[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
-[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
-[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
-[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
-[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
-[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
-[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
-[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
-[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
-[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
-[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
-[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
-[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
-[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
-[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
-[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
-[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
-[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
-[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
-[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
-[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
-[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
-[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
-[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
-[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
-[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
-[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
-[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
-[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
-[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
-[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
-[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
-[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
-[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
-[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
-[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
-[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
-[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
-[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
-[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
-[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
-[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
-[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
-[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
-[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
-[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
-[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
-[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
-[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
-[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
-[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
-[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
-[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
-[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
-[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
-[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
-[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
-[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
-[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
-[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
-[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
-[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
-[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
-[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
-[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
-[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
-[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
-[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
-[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
-[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
-[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
-[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
-[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
-[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
-[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
-[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
-[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
-[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
-[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
-[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
-[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
-[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
-[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
-[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
-[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
-[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
-[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
-[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
-[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.d b/gas/testsuite/gas/riscv/cv-bi-beqimm.d
deleted file mode 100644
index 97ef57d91cc..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-beqimm.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvbi
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <foo>:
-[ ]+0:[ ]+0102e00b[ ]+cv.beqimm[ ]+t0,-16,0 +<foo>
-[ ]+4:[ ]+fe5eee8b[ ]+cv.beqimm[ ]+t4,5,0 +<foo>
-[ ]+8:[ ]+fef3ec8b[ ]+cv.beqimm[ ]+t2,15,0 +<foo>
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.d b/gas/testsuite/gas/riscv/cv-bi-bneimm.d
deleted file mode 100644
index 7dddf408107..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-bneimm.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvbi
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <foo>:
-[ ]+0:[ ]+0102f00b[ ]+cv.bneimm[ ]+t0,-16,0 +<foo>
-[ ]+4:[ ]+fe5efe8b[ ]+cv.bneimm[ ]+t4,5,0 +<foo>
-[ ]+8:[ ]+fef3fc8b[ ]+cv.bneimm[ ]+t2,15,0 +<foo>
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.s b/gas/testsuite/gas/riscv/cv-bi-bneimm.s
deleted file mode 100644
index 8014e6a8a4f..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-bneimm.s
+++ /dev/null
@@ -1,4 +0,0 @@
-foo:
- cv.bneimm t0, -16, foo
- cv.bneimm t4, 5, foo
- cv.bneimm t2, 15, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.d b/gas/testsuite/gas/riscv/cv-bi-fail-march.d
deleted file mode 100644
index 7a24146afe2..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-march.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i
-#source: cv-bi-fail-march.s
-#error_output: cv-bi-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.l b/gas/testsuite/gas/riscv/cv-bi-fail-march.l
deleted file mode 100644
index c351c64d414..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-march.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required
-.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.s b/gas/testsuite/gas/riscv/cv-bi-fail-march.s
deleted file mode 100644
index b7fa16de240..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-march.s
+++ /dev/null
@@ -1,5 +0,0 @@
-# Absence of xcorev or xcorevbi march option disables all CORE-V
-# immediate branching extensions.
-foo:
- cv.beqimm t2, 1, foo
- cv.bneimm t2, 1, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
deleted file mode 100644
index cc73fdd6492..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvbi
-#source: cv-bi-fail-operand-01.s
-#error_output: cv-bi-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
deleted file mode 100644
index c76c5139429..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.beqimm 20,10,foo'
-.*: Error: illegal operands `cv.bneimm 8,-4,foo'
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
deleted file mode 100644
index 7c529d4d045..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
+++ /dev/null
@@ -1,4 +0,0 @@
-# Comparison target must be a register
-foo:
- cv.beqimm 20, 10, foo
- cv.bneimm 8, -4, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
deleted file mode 100644
index 39741b9ed2b..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvbi
-#source: cv-bi-fail-operand-02.s
-#error_output: cv-bi-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
deleted file mode 100644
index 7c766fb072a..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*: Error: instruction cv.beqimm requires absolute expression
-.*: Error: instruction cv.bneimm requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
deleted file mode 100644
index 5c8874cb9ac..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
+++ /dev/null
@@ -1,4 +0,0 @@
-# Comparison value must be an immediate
-foo:
- cv.beqimm t0, t1, foo
- cv.bneimm t3, t4, foo
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
deleted file mode 100644
index 141efdeacc6..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvbi
-#source: cv-bi-fail-operand-03.s
-#error_output: cv-bi-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
deleted file mode 100644
index af8ebce1284..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
+++ /dev/null
@@ -1,9 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.beqimm t0,-17,foo'
-.*: Error: illegal operands `cv.beqimm t2,-32,foo'
-.*: Error: illegal operands `cv.beqimm t4,16,foo'
-.*: Error: illegal operands `cv.beqimm t3,44,foo'
-.*: Error: illegal operands `cv.bneimm t0,-17,foo'
-.*: Error: illegal operands `cv.bneimm t2,-32,foo'
-.*: Error: illegal operands `cv.bneimm t4,16,foo'
-.*: Error: illegal operands `cv.bneimm t3,44,foo'
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
deleted file mode 100644
index 9c7f67b4aed..00000000000
--- a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# Comparison value must be an immediate in range [-16, +15]
-foo:
- cv.beqimm t0, -17, foo
- cv.beqimm t2, -32, foo
- cv.beqimm t4, 16, foo
- cv.beqimm t3, 44, foo
- cv.bneimm t0, -17, foo
- cv.bneimm t2, -32, foo
- cv.bneimm t4, 16, foo
- cv.bneimm t3, 44, foo
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.d b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
deleted file mode 100644
index 5a3a6dba66b..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-fail-march.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i
-#source: cv-elw-fail-march.s
-#error_output: cv-elw-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.s b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
deleted file mode 100644
index 57848849a36..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-fail-march.s
+++ /dev/null
@@ -1,41 +0,0 @@
-target:
- # Immediate Boundary Tests
- cv.elw x5,-2048(x6)
- cv.elw x5,0(x6)
- cv.elw x5,20(x6)
- cv.elw x5,2047(x6)
- cv.elw x31,2047(x31)
-
- # Register Boundary Tests
- cv.elw x0,0(x0)
- cv.elw x1,1024(x1)
- cv.elw x2,1024(x2)
- cv.elw x3,1024(x3)
- cv.elw x4,1024(x4)
- cv.elw x5,1024(x5)
- cv.elw x6,1024(x6)
- cv.elw x7,1024(x7)
- cv.elw x8,1024(x8)
- cv.elw x9,1024(x9)
- cv.elw x10,1024(x10)
- cv.elw x11,1024(x11)
- cv.elw x12,1024(x12)
- cv.elw x13,1024(x13)
- cv.elw x14,1024(x14)
- cv.elw x15,1024(x15)
- cv.elw x16,1024(x16)
- cv.elw x17,1024(x17)
- cv.elw x18,1024(x18)
- cv.elw x19,1024(x19)
- cv.elw x20,1024(x20)
- cv.elw x21,1024(x21)
- cv.elw x22,1024(x22)
- cv.elw x23,1024(x23)
- cv.elw x24,1024(x24)
- cv.elw x25,1024(x25)
- cv.elw x26,1024(x26)
- cv.elw x27,1024(x27)
- cv.elw x28,1024(x28)
- cv.elw x29,1024(x29)
- cv.elw x30,1024(x30)
- cv.elw x31,1024(x31)
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d b/gas/testsuite/gas/riscv/cv-elw-fail.d
deleted file mode 100644
index d7fd1d1a6cb..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-fail.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvelw
-#source: cv-elw-fail.s
-#error_output: cv-elw-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l b/gas/testsuite/gas/riscv/cv-elw-fail.l
deleted file mode 100644
index 4d3f15ba138..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-fail.l
+++ /dev/null
@@ -1,5 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.elw x5,-2049\(x6\)'
-.*: Error: illegal operands `cv.elw x5,2048\(x6\)'
-.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)'
-.*: Error: illegal operands `cv.elw x32,1024\(x32\)'
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s b/gas/testsuite/gas/riscv/cv-elw-fail.s
deleted file mode 100644
index 4ce122297f4..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-fail.s
+++ /dev/null
@@ -1,8 +0,0 @@
-target:
- # Immediate Boundary Tests
- cv.elw x5,-2049(x6)
- cv.elw x5,2048(x6)
-
- # Register Boundary Tests
- cv.elw x-1,1024(x-1)
- cv.elw x32,1024(x32)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d b/gas/testsuite/gas/riscv/cv-elw-pass.d
deleted file mode 100644
index 04511491d18..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-pass.d
+++ /dev/null
@@ -1,46 +0,0 @@
-#as: -march=rv32i_xcvelw
-#source: cv-elw-pass.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003628b[ ]+cv.elw[ ]+t0,-2048\(t1\)
-[ ]+4:[ ]+0003628b[ ]+cv.elw[ ]+t0,0\(t1\)
-[ ]+8:[ ]+0143628b[ ]+cv.elw[ ]+t0,20\(t1\)
-[ ]+c:[ ]+7ff3628b[ ]+cv.elw[ ]+t0,2047\(t1\)
-[ ]+10:[ ]+7fffef8b[ ]+cv.elw[ ]+t6,2047\(t6\)
-[ ]+14:[ ]+0000600b[ ]+cv.elw[ ]+zero,0\(zero\) # 0 <target>
-[ ]+18:[ ]+4000e08b[ ]+cv.elw[ ]+ra,1024\(ra\)
-[ ]+1c:[ ]+4001610b[ ]+cv.elw[ ]+sp,1024\(sp\)
-[ ]+20:[ ]+4001e18b[ ]+cv.elw[ ]+gp,1024\(gp\)
-[ ]+24:[ ]+4002620b[ ]+cv.elw[ ]+tp,1024\(tp\) # 400 <target\+0x400>
-[ ]+28:[ ]+4002e28b[ ]+cv.elw[ ]+t0,1024\(t0\)
-[ ]+2c:[ ]+4003630b[ ]+cv.elw[ ]+t1,1024\(t1\)
-[ ]+30:[ ]+4003e38b[ ]+cv.elw[ ]+t2,1024\(t2\)
-[ ]+34:[ ]+4004640b[ ]+cv.elw[ ]+s0,1024\(s0\)
-[ ]+38:[ ]+4004e48b[ ]+cv.elw[ ]+s1,1024\(s1\)
-[ ]+3c:[ ]+4005650b[ ]+cv.elw[ ]+a0,1024\(a0\)
-[ ]+40:[ ]+4005e58b[ ]+cv.elw[ ]+a1,1024\(a1\)
-[ ]+44:[ ]+4006660b[ ]+cv.elw[ ]+a2,1024\(a2\)
-[ ]+48:[ ]+4006e68b[ ]+cv.elw[ ]+a3,1024\(a3\)
-[ ]+4c:[ ]+4007670b[ ]+cv.elw[ ]+a4,1024\(a4\)
-[ ]+50:[ ]+4007e78b[ ]+cv.elw[ ]+a5,1024\(a5\)
-[ ]+54:[ ]+4008680b[ ]+cv.elw[ ]+a6,1024\(a6\)
-[ ]+58:[ ]+4008e88b[ ]+cv.elw[ ]+a7,1024\(a7\)
-[ ]+5c:[ ]+4009690b[ ]+cv.elw[ ]+s2,1024\(s2\)
-[ ]+60:[ ]+4009e98b[ ]+cv.elw[ ]+s3,1024\(s3\)
-[ ]+64:[ ]+400a6a0b[ ]+cv.elw[ ]+s4,1024\(s4\)
-[ ]+68:[ ]+400aea8b[ ]+cv.elw[ ]+s5,1024\(s5\)
-[ ]+6c:[ ]+400b6b0b[ ]+cv.elw[ ]+s6,1024\(s6\)
-[ ]+70:[ ]+400beb8b[ ]+cv.elw[ ]+s7,1024\(s7\)
-[ ]+74:[ ]+400c6c0b[ ]+cv.elw[ ]+s8,1024\(s8\)
-[ ]+78:[ ]+400cec8b[ ]+cv.elw[ ]+s9,1024\(s9\)
-[ ]+7c:[ ]+400d6d0b[ ]+cv.elw[ ]+s10,1024\(s10\)
-[ ]+80:[ ]+400ded8b[ ]+cv.elw[ ]+s11,1024\(s11\)
-[ ]+84:[ ]+400e6e0b[ ]+cv.elw[ ]+t3,1024\(t3\)
-[ ]+88:[ ]+400eee8b[ ]+cv.elw[ ]+t4,1024\(t4\)
-[ ]+8c:[ ]+400f6f0b[ ]+cv.elw[ ]+t5,1024\(t5\)
-[ ]+90:[ ]+400fef8b[ ]+cv.elw[ ]+t6,1024\(t6\)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s b/gas/testsuite/gas/riscv/cv-elw-pass.s
deleted file mode 100644
index 57848849a36..00000000000
--- a/gas/testsuite/gas/riscv/cv-elw-pass.s
+++ /dev/null
@@ -1,41 +0,0 @@
-target:
- # Immediate Boundary Tests
- cv.elw x5,-2048(x6)
- cv.elw x5,0(x6)
- cv.elw x5,20(x6)
- cv.elw x5,2047(x6)
- cv.elw x31,2047(x31)
-
- # Register Boundary Tests
- cv.elw x0,0(x0)
- cv.elw x1,1024(x1)
- cv.elw x2,1024(x2)
- cv.elw x3,1024(x3)
- cv.elw x4,1024(x4)
- cv.elw x5,1024(x5)
- cv.elw x6,1024(x6)
- cv.elw x7,1024(x7)
- cv.elw x8,1024(x8)
- cv.elw x9,1024(x9)
- cv.elw x10,1024(x10)
- cv.elw x11,1024(x11)
- cv.elw x12,1024(x12)
- cv.elw x13,1024(x13)
- cv.elw x14,1024(x14)
- cv.elw x15,1024(x15)
- cv.elw x16,1024(x16)
- cv.elw x17,1024(x17)
- cv.elw x18,1024(x18)
- cv.elw x19,1024(x19)
- cv.elw x20,1024(x20)
- cv.elw x21,1024(x21)
- cv.elw x22,1024(x22)
- cv.elw x23,1024(x23)
- cv.elw x24,1024(x24)
- cv.elw x25,1024(x25)
- cv.elw x26,1024(x26)
- cv.elw x27,1024(x27)
- cv.elw x28,1024(x28)
- cv.elw x29,1024(x29)
- cv.elw x30,1024(x30)
- cv.elw x31,1024(x31)
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.d b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
deleted file mode 100644
index eb6352f85f2..00000000000
--- a/gas/testsuite/gas/riscv/cv-mac-fail-march.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i
-#source: cv-mac-fail-march.s
-#error_output: cv-mac-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.l b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
deleted file mode 100644
index d2bc12c804a..00000000000
--- a/gas/testsuite/gas/riscv/cv-mac-fail-march.l
+++ /dev/null
@@ -1,23 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension `xcvmac' required
-.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension `xcvmac' required
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.s b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
deleted file mode 100644
index 78b08423a64..00000000000
--- a/gas/testsuite/gas/riscv/cv-mac-fail-march.s
+++ /dev/null
@@ -1,24 +0,0 @@
-# Absence of the xcvmac march option disables all CORE-V MAC extensions.
-target:
- cv.mac t4, t2, t0
- cv.msu t4, t2, t0
- cv.muls t4, t2, t0
- cv.mulhhs t4, t2, t0
- cv.mulsn t4, t2, t0, 4
- cv.mulhhsn t4, t2, t0, 16
- cv.mulsrn t4, t2, t0, 10
- cv.mulhhsrn t4, t2, t0, 17
- cv.mulu t4, t2, t0
- cv.mulhhu t4, t2, t0
- cv.mulun t4, t2, t0, 7
- cv.mulhhun t4, t2, t0, 16
- cv.mulurn t4, t2, t0, 11
- cv.mulhhurn t4, t2, t0, 9
- cv.macsn t4, t2, t0, 24
- cv.machhsn t4, t2, t0, 11
- cv.macsrn t4, t2, t0, 9
- cv.machhsrn t4, t2, t0, 24
- cv.macun t4, t2, t0, 27
- cv.machhun t4, t2, t0, 18
- cv.macurn t4, t2, t0, 25
- cv.machhurn t4, t2, t0, 5
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
deleted file mode 100644
index 51e1b3052c9..00000000000
--- a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmac
-#source: cv-mac-fail-operand.s
-#error_output: cv-mac-fail-operand.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.d b/gas/testsuite/gas/riscv/cv-mac-insns.d
deleted file mode 100644
index 9a961051a97..00000000000
--- a/gas/testsuite/gas/riscv/cv-mac-insns.d
+++ /dev/null
@@ -1,87 +0,0 @@
-#as: -march=rv32i_xcvmac
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
-[ ]+4:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
-[ ]+8:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
-[ ]+c:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
-[ ]+10:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
-[ ]+14:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
-[ ]+18:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
-[ ]+1c:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
-[ ]+20:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
-[ ]+24:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
-[ ]+28:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
-[ ]+2c:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
-[ ]+30:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
-[ ]+34:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
-[ ]+38:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
-[ ]+3c:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
-[ ]+40:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
-[ ]+44:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
-[ ]+48:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
-[ ]+4c:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
-[ ]+50:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
-[ ]+54:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
-[ ]+58:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
-[ ]+5c:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
-[ ]+60:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
-[ ]+64:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
-[ ]+68:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
-[ ]+6c:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
-[ ]+70:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
-[ ]+74:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
-[ ]+78:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
-[ ]+7c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
-[ ]+80:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
-[ ]+84:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
-[ ]+88:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
-[ ]+8c:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
-[ ]+90:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
-[ ]+94:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
-[ ]+98:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
-[ ]+9c:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
-[ ]+a0:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
-[ ]+a4:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
-[ ]+a8:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
-[ ]+ac:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
-[ ]+b0:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
-[ ]+b4:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
-[ ]+b8:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
-[ ]+bc:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
-[ ]+c0:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
-[ ]+c4:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
-[ ]+c8:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
-[ ]+cc:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
-[ ]+d0:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
-[ ]+d4:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
-[ ]+d8:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
-[ ]+dc:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
-[ ]+e0:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
-[ ]+e4:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
-[ ]+e8:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
-[ ]+ec:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
-[ ]+f0:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
-[ ]+f4:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
-[ ]+f8:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
-[ ]+fc:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
-[ ]+100:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
-[ ]+104:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
-[ ]+108:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
-[ ]+10c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
-[ ]+110:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
-[ ]+114:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
-[ ]+118:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
-[ ]+11c:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
-[ ]+120:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
-[ ]+124:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
-[ ]+128:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
-[ ]+12c:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
-[ ]+130:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
-[ ]+134:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.d b/gas/testsuite/gas/riscv/cv-mem-fail-march.d
deleted file mode 100644
index a2dff75937b..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-march.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i
-#source: cv-mem-fail-march.s
-#error_output: cv-mem-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.l b/gas/testsuite/gas/riscv/cv-mem-fail-march.l
deleted file mode 100644
index 4c331344d26..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-march.l
+++ /dev/null
@@ -1,25 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `cv.lb t4,t2\(t0\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lbu t6,t1\(t4\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lh t2,t0\(t3\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lhu t0,t5\(t1\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lw t1,t3\(t6\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lb t4,\(t0\),t2', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),t1', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lh t2,\(t3\),t0', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),t5', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lw t1,\(t6\),t3', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lb t4,\(t0\),23', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),0', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lh t2,\(t3\),77', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),101', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.lw t1,\(t6\),6', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sb t0,t1\(t2\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sh t1,t3\(t4\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sw t1,t2\(t4\)', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sb t0,\(t2\),t1', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sh t1,\(t2\),t6', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sw t5,\(t2\),t6', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sb t6,\(t1\),10', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sh t3,\(t5\),80', extension `xcvmem' required
-.*: Error: unrecognized opcode `cv.sw t1,\(t4\),20', extension `xcvmem' required
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-march.s b/gas/testsuite/gas/riscv/cv-mem-fail-march.s
deleted file mode 100644
index cd82d26a7c5..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-march.s
+++ /dev/null
@@ -1,26 +0,0 @@
-# Absence of xcvmem march option disables all CORE-V mem extensions
-target:
- cv.lb t4, t2(t0)
- cv.lbu t6, t1(t4)
- cv.lh t2, t0(t3)
- cv.lhu t0, t5(t1)
- cv.lw t1, t3(t6)
- cv.lb t4, (t0), t2
- cv.lbu t6, (t4), t1
- cv.lh t2, (t3), t0
- cv.lhu t0, (t1), t5
- cv.lw t1, (t6), t3
- cv.lb t4, (t0), 23
- cv.lbu t6, (t4), 0
- cv.lh t2, (t3), 77
- cv.lhu t0, (t1), 101
- cv.lw t1, (t6), 6
- cv.sb t0, t1(t2)
- cv.sh t1, t3(t4)
- cv.sw t1, t2(t4)
- cv.sb t0, (t2), t1
- cv.sh t1, (t2), t6
- cv.sw t5, (t2), t6
- cv.sb t6, (t1), 10
- cv.sh t3, (t5), 80
- cv.sw t1, (t4), 20
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
deleted file mode 100644
index f1bb6120ab6..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmem
-#source: cv-mem-fail-operand-01.s
-#error_output: cv-mem-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
deleted file mode 100644
index 839929118a0..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
+++ /dev/null
@@ -1,21 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.lb 20,10\(t1\)'
-.*: Error: illegal operands `cv.lb 32,\(t2\),15'
-.*: Error: illegal operands `cv.lb 40,t2\(t3\)'
-.*: Error: illegal operands `cv.lb 28,\(t4\),t3'
-.*: Error: illegal operands `cv.lbu 16,20\(t5\)'
-.*: Error: illegal operands `cv.lbu 20,\(t6\),30'
-.*: Error: illegal operands `cv.lbu 44,t4\(t1\)'
-.*: Error: illegal operands `cv.lbu 48,\(t2\),t5'
-.*: Error: illegal operands `cv.lh 52,25\(t3\)'
-.*: Error: illegal operands `cv.lh 12,\(t4\),10'
-.*: Error: illegal operands `cv.lh 16,t6\(t5\)'
-.*: Error: illegal operands `cv.lh 36,\(t6\),t1'
-.*: Error: illegal operands `cv.lhu 24,35\(t1\)'
-.*: Error: illegal operands `cv.lhu 12,\(t2\),13'
-.*: Error: illegal operands `cv.lhu 32,t2\(t3\)'
-.*: Error: illegal operands `cv.lhu 40,\(t4\),t3'
-.*: Error: illegal operands `cv.lw 44,18\(t5\)'
-.*: Error: illegal operands `cv.lw 48,\(t6\),8'
-.*: Error: illegal operands `cv.lw 24,t4\(t1\)'
-.*: Error: illegal operands `cv.lw 12,\(t2\),t5'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
deleted file mode 100644
index 385b3f79704..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
+++ /dev/null
@@ -1,22 +0,0 @@
-# Destination operand must be a register
-target:
- cv.lb 20, 10(t1)
- cv.lb 32, (t2), 15
- cv.lb 40, t2(t3)
- cv.lb 28, (t4), t3
- cv.lbu 16, 20(t5)
- cv.lbu 20, (t6), 30
- cv.lbu 44, t4(t1)
- cv.lbu 48, (t2), t5
- cv.lh 52, 25(t3)
- cv.lh 12, (t4), 10
- cv.lh 16, t6(t5)
- cv.lh 36, (t6), t1
- cv.lhu 24, 35(t1)
- cv.lhu 12, (t2), 13
- cv.lhu 32, t2(t3)
- cv.lhu 40, (t4), t3
- cv.lw 44, 18(t5)
- cv.lw 48, (t6), 8
- cv.lw 24, t4(t1)
- cv.lw 12, (t2), t5
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
deleted file mode 100644
index bbf723736f8..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmem
-#source: cv-mem-fail-operand-02.s
-#error_output: cv-mem-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
deleted file mode 100644
index 871a221ea6d..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
+++ /dev/null
@@ -1,13 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.sb 12,10\(t1\)'
-.*: Error: illegal operands `cv.sb 14,\(t2\),20'
-.*: Error: illegal operands `cv.sb 16,t1\(t3\)'
-.*: Error: illegal operands `cv.sb 20,\(t4\),t2'
-.*: Error: illegal operands `cv.sh 30,30\(t5\)'
-.*: Error: illegal operands `cv.sh 15,\(t6\),40'
-.*: Error: illegal operands `cv.sh 45,t3\(t1\)'
-.*: Error: illegal operands `cv.sh 52,\(t2\),t4'
-.*: Error: illegal operands `cv.sw 12,12\(t3\)'
-.*: Error: illegal operands `cv.sw 10,\(t4\),16'
-.*: Error: illegal operands `cv.sw 82,t5\(t5\)'
-.*: Error: illegal operands `cv.sw 14,\(t1\),t6'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
deleted file mode 100644
index 8d7a41f6323..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
+++ /dev/null
@@ -1,14 +0,0 @@
-# Source operand must be a register
-target:
- cv.sb 12, 10(t1)
- cv.sb 14, (t2), 20
- cv.sb 16, t1(t3)
- cv.sb 20, (t4), t2
- cv.sh 30, 30(t5)
- cv.sh 15, (t6), 40
- cv.sh 45, t3(t1)
- cv.sh 52, (t2), t4
- cv.sw 12, 12(t3)
- cv.sw 10, (t4), 16
- cv.sw 82, t5(t5)
- cv.sw 14, (t1), t6
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
deleted file mode 100644
index 653c30a3321..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmem
-#source: cv-mem-fail-operand-03.s
-#error_output: cv-mem-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
deleted file mode 100644
index 4ffdbb318cc..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
+++ /dev/null
@@ -1,33 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.sb t0,10\(12\)'
-.*: Error: illegal operands `cv.sb t1,\(24\),20'
-.*: Error: illegal operands `cv.sb t2,t1\(25\)'
-.*: Error: illegal operands `cv.sb t3,\(75\),t2'
-.*: Error: illegal operands `cv.sh t4,30\(13\)'
-.*: Error: illegal operands `cv.sh t5,\(16\),40'
-.*: Error: illegal operands `cv.sh t6,t3\(31\)'
-.*: Error: illegal operands `cv.sh t0,\(37\),t4'
-.*: Error: illegal operands `cv.sw t1,12\(51\)'
-.*: Error: illegal operands `cv.sw t2,\(43\),16'
-.*: Error: illegal operands `cv.sw t3,t5\(61\)'
-.*: Error: illegal operands `cv.sw t4,\(67\),t6'
-.*: Error: illegal operands `cv.lb t0,12\(12\)'
-.*: Error: illegal operands `cv.lb t1,\(24\),13'
-.*: Error: illegal operands `cv.lb t2,t3\(25\)'
-.*: Error: illegal operands `cv.lb t3,\(75\),t4'
-.*: Error: illegal operands `cv.lbu t4,22\(51\)'
-.*: Error: illegal operands `cv.lbu t5,\(43\),10'
-.*: Error: illegal operands `cv.lbu t6,t5\(61\)'
-.*: Error: illegal operands `cv.lbu t0,\(67\),t6'
-.*: Error: illegal operands `cv.lh t1,19\(13\)'
-.*: Error: illegal operands `cv.lh t2,\(16\),41'
-.*: Error: illegal operands `cv.lh t3,t0\(31\)'
-.*: Error: illegal operands `cv.lh t4,\(37\),t1'
-.*: Error: illegal operands `cv.lhu t5,15\(14\)'
-.*: Error: illegal operands `cv.lhu t6,\(17\),12'
-.*: Error: illegal operands `cv.lhu t0,t2\(14\)'
-.*: Error: illegal operands `cv.lhu t1,\(39\),t3'
-.*: Error: illegal operands `cv.lw t2,4\(24\)'
-.*: Error: illegal operands `cv.lw t3,\(21\),6'
-.*: Error: illegal operands `cv.lw t5,t4\(16\)'
-.*: Error: illegal operands `cv.lw t4,\(47\),t5'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
deleted file mode 100644
index e2e40921f98..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
+++ /dev/null
@@ -1,34 +0,0 @@
-# Base operand must be a register
-target:
- cv.sb t0, 10(12)
- cv.sb t1, (24), 20
- cv.sb t2, t1(25)
- cv.sb t3, (75), t2
- cv.sh t4, 30(13)
- cv.sh t5, (16), 40
- cv.sh t6, t3(31)
- cv.sh t0, (37), t4
- cv.sw t1, 12(51)
- cv.sw t2, (43), 16
- cv.sw t3, t5(61)
- cv.sw t4, (67), t6
- cv.lb t0, 12(12)
- cv.lb t1, (24), 13
- cv.lb t2, t3(25)
- cv.lb t3, (75), t4
- cv.lbu t4, 22(51)
- cv.lbu t5, (43), 10
- cv.lbu t6, t5(61)
- cv.lbu t0, (67), t6
- cv.lh t1, 19(13)
- cv.lh t2, (16), 41
- cv.lh t3, t0(31)
- cv.lh t4, (37), t1
- cv.lhu t5, 15(14)
- cv.lhu t6, (17), 12
- cv.lhu t0, t2(14)
- cv.lhu t1, (39), t3
- cv.lw t2, 4(24)
- cv.lw t3, (21), 6
- cv.lw t5, t4(16)
- cv.lw t4, (47), t5
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
deleted file mode 100644
index e6fe3987b99..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmem
-#source: cv-mem-fail-operand-04.s
-#error_output: cv-mem-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
deleted file mode 100644
index a6d072291fc..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
+++ /dev/null
@@ -1,41 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.lb t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.lb t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.lbu t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.lbu t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.lh t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.lh t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.lhu t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.lhu t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.lw t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.lw t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.lb t2,-3678\(t1\)'
-.*: Error: illegal operands `cv.lb t2,\(t1\),-3678'
-.*: Error: illegal operands `cv.lbu t2,-3678\(t1\)'
-.*: Error: illegal operands `cv.lbu t2,\(t1\),-3678'
-.*: Error: illegal operands `cv.lh t2,-3678\(t1\)'
-.*: Error: illegal operands `cv.lh t2,\(t1\),-3678'
-.*: Error: illegal operands `cv.lhu t2,-3678\(t1\)'
-.*: Error: illegal operands `cv.lhu t2,\(t1\),-3678'
-.*: Error: illegal operands `cv.lw t2,-3678\(t1\)'
-.*: Error: illegal operands `cv.lw t2,\(t1\),-3678'
-.*: Error: illegal operands `cv.lb t2,2048\(t1\)'
-.*: Error: illegal operands `cv.lb t2,\(t1\),2048'
-.*: Error: illegal operands `cv.lbu t2,2048\(t1\)'
-.*: Error: illegal operands `cv.lbu t2,\(t1\),2048'
-.*: Error: illegal operands `cv.lh t2,2048\(t1\)'
-.*: Error: illegal operands `cv.lh t2,\(t1\),2048'
-.*: Error: illegal operands `cv.lhu t2,2048\(t1\)'
-.*: Error: illegal operands `cv.lhu t2,\(t1\),2048'
-.*: Error: illegal operands `cv.lw t2,2048\(t1\)'
-.*: Error: illegal operands `cv.lw t2,\(t1\),2048'
-.*: Error: illegal operands `cv.lb t2,4595\(t1\)'
-.*: Error: illegal operands `cv.lb t2,\(t1\),4595'
-.*: Error: illegal operands `cv.lbu t2,4595\(t1\)'
-.*: Error: illegal operands `cv.lbu t2,\(t1\),4595'
-.*: Error: illegal operands `cv.lh t2,4595\(t1\)'
-.*: Error: illegal operands `cv.lh t2,\(t1\),4595'
-.*: Error: illegal operands `cv.lhu t2,4595\(t1\)'
-.*: Error: illegal operands `cv.lhu t2,\(t1\),4595'
-.*: Error: illegal operands `cv.lw t2,4595\(t1\)'
-.*: Error: illegal operands `cv.lw t2,\(t1\),4595'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
deleted file mode 100644
index a6307cee49d..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
+++ /dev/null
@@ -1,42 +0,0 @@
-# Offset operand must be in range [-2048, 2047]
-target:
- cv.lb t2, -2049(t1)
- cv.lb t2, (t1), -2049
- cv.lbu t2, -2049(t1)
- cv.lbu t2, (t1), -2049
- cv.lh t2, -2049(t1)
- cv.lh t2, (t1), -2049
- cv.lhu t2, -2049(t1)
- cv.lhu t2, (t1), -2049
- cv.lw t2, -2049(t1)
- cv.lw t2, (t1), -2049
- cv.lb t2, -3678(t1)
- cv.lb t2, (t1), -3678
- cv.lbu t2, -3678(t1)
- cv.lbu t2, (t1), -3678
- cv.lh t2, -3678(t1)
- cv.lh t2, (t1), -3678
- cv.lhu t2, -3678(t1)
- cv.lhu t2, (t1), -3678
- cv.lw t2, -3678(t1)
- cv.lw t2, (t1), -3678
- cv.lb t2, 2048(t1)
- cv.lb t2, (t1), 2048
- cv.lbu t2, 2048(t1)
- cv.lbu t2, (t1), 2048
- cv.lh t2, 2048(t1)
- cv.lh t2, (t1), 2048
- cv.lhu t2, 2048(t1)
- cv.lhu t2, (t1), 2048
- cv.lw t2, 2048(t1)
- cv.lw t2, (t1), 2048
- cv.lb t2, 4595(t1)
- cv.lb t2, (t1), 4595
- cv.lbu t2, 4595(t1)
- cv.lbu t2, (t1), 4595
- cv.lh t2, 4595(t1)
- cv.lh t2, (t1), 4595
- cv.lhu t2, 4595(t1)
- cv.lhu t2, (t1), 4595
- cv.lw t2, 4595(t1)
- cv.lw t2, (t1), 4595
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
deleted file mode 100644
index c00880fa119..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32i_xcvmem
-#source: cv-mem-fail-operand-05.s
-#error_output: cv-mem-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
deleted file mode 100644
index 3069f54cc3a..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
+++ /dev/null
@@ -1,25 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cv.sb t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.sb t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.sh t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.sh t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.sw t2,-2049\(t1\)'
-.*: Error: illegal operands `cv.sw t2,\(t1\),-2049'
-.*: Error: illegal operands `cv.sb t2,-3669\(t1\)'
-.*: Error: illegal operands `cv.sb t2,\(t1\),-3669'
-.*: Error: illegal operands `cv.sh t2,-3669\(t1\)'
-.*: Error: illegal operands `cv.sh t2,\(t1\),-3669'
-.*: Error: illegal operands `cv.sw t2,-3669\(t1\)'
-.*: Error: illegal operands `cv.sw t2,\(t1\),-3669'
-.*: Error: illegal operands `cv.sb t2,2048\(t1\)'
-.*: Error: illegal operands `cv.sb t2,\(t1\),2048'
-.*: Error: illegal operands `cv.sh t2,2048\(t1\)'
-.*: Error: illegal operands `cv.sh t2,\(t1\),2048'
-.*: Error: illegal operands `cv.sw t2,2048\(t1\)'
-.*: Error: illegal operands `cv.sw t2,\(t1\),2048'
-.*: Error: illegal operands `cv.sb t2,5341\(t1\)'
-.*: Error: illegal operands `cv.sb t2,\(t1\),5341'
-.*: Error: illegal operands `cv.sh t2,5341\(t1\)'
-.*: Error: illegal operands `cv.sh t2,\(t1\),5341'
-.*: Error: illegal operands `cv.sw t2,5341\(t1\)'
-.*: Error: illegal operands `cv.sw t2,\(t1\),5341'
diff --git a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
deleted file mode 100644
index 33b5883bc64..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
+++ /dev/null
@@ -1,26 +0,0 @@
-# Offset operand must be in range [-2048, 2047]
-target:
- cv.sb t2, -2049(t1)
- cv.sb t2, (t1), -2049
- cv.sh t2, -2049(t1)
- cv.sh t2, (t1), -2049
- cv.sw t2, -2049(t1)
- cv.sw t2, (t1), -2049
- cv.sb t2, -3669(t1)
- cv.sb t2, (t1), -3669
- cv.sh t2, -3669(t1)
- cv.sh t2, (t1), -3669
- cv.sw t2, -3669(t1)
- cv.sw t2, (t1), -3669
- cv.sb t2, 2048(t1)
- cv.sb t2, (t1), 2048
- cv.sh t2, 2048(t1)
- cv.sh t2, (t1), 2048
- cv.sw t2, 2048(t1)
- cv.sw t2, (t1), 2048
- cv.sb t2, 5341(t1)
- cv.sb t2, (t1), 5341
- cv.sh t2, 5341(t1)
- cv.sh t2, (t1), 5341
- cv.sw t2, 5341(t1)
- cv.sw t2, (t1), 5341
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbpost.d b/gas/testsuite/gas/riscv/cv-mem-lbpost.d
deleted file mode 100644
index 9e3dbd6d345..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003828b[ ]+cv.lb[ ]+t0,\(t2\),-2048
-[ ]+4:[ ]+00f30e8b[ ]+cv.lb[ ]+t4,\(t1\),15
-[ ]+8:[ ]+7fff0e0b[ ]+cv.lb[ ]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbpost.s b/gas/testsuite/gas/riscv/cv-mem-lbpost.s
deleted file mode 100644
index a55a414bb31..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lb t0, (t2), -2048
- cv.lb t4, (t1), 15
- cv.lb t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrr.d b/gas/testsuite/gas/riscv/cv-mem-lbrr.d
deleted file mode 100644
index 6183ac47a86..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0863b2ab[ ]+cv.lb[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+09c33eab[ ]+cv.lb[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+085f3e2b[ ]+cv.lb[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrr.s b/gas/testsuite/gas/riscv/cv-mem-lbrr.s
deleted file mode 100644
index 1cfaf241db3..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lb t0, t1(t2)
- cv.lb t4, t3(t1)
- cv.lb t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
deleted file mode 100644
index 839915ea45b..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0063b2ab[ ]+cv.lb[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+01c33eab[ ]+cv.lb[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+005f3e2b[ ]+cv.lb[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
deleted file mode 100644
index 48f71ce31f1..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lb t0, (t2), t1
- cv.lb t4, (t1), t3
- cv.lb t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbupost.d b/gas/testsuite/gas/riscv/cv-mem-lbupost.d
deleted file mode 100644
index 0db23ad5ecd..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbupost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003c28b[ ]+cv.lbu[ ]+t0,\(t2\),-2048
-[ ]+4:[ ]+00f34e8b[ ]+cv.lbu[ ]+t4,\(t1\),15
-[ ]+8:[ ]+7fff4e0b[ ]+cv.lbu[ ]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lbupost.s b/gas/testsuite/gas/riscv/cv-mem-lbupost.s
deleted file mode 100644
index e4d2ba8f805..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lbupost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lbu t0, (t2), -2048
- cv.lbu t4, (t1), 15
- cv.lbu t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburr.d b/gas/testsuite/gas/riscv/cv-mem-lburr.d
deleted file mode 100644
index 12fe6b07f40..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lburr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+1863b2ab[ ]+cv.lbu[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+19c33eab[ ]+cv.lbu[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+185f3e2b[ ]+cv.lbu[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburr.s b/gas/testsuite/gas/riscv/cv-mem-lburr.s
deleted file mode 100644
index 20982b1b3bd..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lburr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lbu t0, t1(t2)
- cv.lbu t4, t3(t1)
- cv.lbu t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburrpost.d b/gas/testsuite/gas/riscv/cv-mem-lburrpost.d
deleted file mode 100644
index 468a1df475b..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lburrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+1063b2ab[ ]+cv.lbu[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+11c33eab[ ]+cv.lbu[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+105f3e2b[ ]+cv.lbu[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lburrpost.s b/gas/testsuite/gas/riscv/cv-mem-lburrpost.s
deleted file mode 100644
index ea23a2faf88..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lburrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lbu t0, (t2), t1
- cv.lbu t4, (t1), t3
- cv.lbu t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhpost.d b/gas/testsuite/gas/riscv/cv-mem-lhpost.d
deleted file mode 100644
index d7ba406fee6..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003928b[ ]+cv.lh[ ]+t0,\(t2\),-2048
-[ ]+4:[ ]+00f31e8b[ ]+cv.lh[ ]+t4,\(t1\),15
-[ ]+8:[ ]+7fff1e0b[ ]+cv.lh[ ]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhpost.s b/gas/testsuite/gas/riscv/cv-mem-lhpost.s
deleted file mode 100644
index 39a3b6f75aa..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lh t0, (t2), -2048
- cv.lh t4, (t1), 15
- cv.lh t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrr.d b/gas/testsuite/gas/riscv/cv-mem-lhrr.d
deleted file mode 100644
index 606af406c01..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0a63b2ab[ ]+cv.lh[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+0bc33eab[ ]+cv.lh[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+0a5f3e2b[ ]+cv.lh[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrr.s b/gas/testsuite/gas/riscv/cv-mem-lhrr.s
deleted file mode 100644
index fe8f761cfce..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lh t0, t1(t2)
- cv.lh t4, t3(t1)
- cv.lh t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
deleted file mode 100644
index d0c9ac0af7b..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0263b2ab[ ]+cv.lh[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+03c33eab[ ]+cv.lh[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+025f3e2b[ ]+cv.lh[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
deleted file mode 100644
index acfc110b8cf..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lh t0, (t2), t1
- cv.lh t4, (t1), t3
- cv.lh t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhupost.d b/gas/testsuite/gas/riscv/cv-mem-lhupost.d
deleted file mode 100644
index 56c15ae9fb9..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhupost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003d28b[ ]+cv.lhu[ ]+t0,\(t2\),-2048
-[ ]+4:[ ]+00f35e8b[ ]+cv.lhu[ ]+t4,\(t1\),15
-[ ]+8:[ ]+7fff5e0b[ ]+cv.lhu[ ]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhupost.s b/gas/testsuite/gas/riscv/cv-mem-lhupost.s
deleted file mode 100644
index 7efa1ac9aca..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhupost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lhu t0, (t2), -2048
- cv.lhu t4, (t1), 15
- cv.lhu t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurr.d b/gas/testsuite/gas/riscv/cv-mem-lhurr.d
deleted file mode 100644
index 9dd81fecc33..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhurr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+1a63b2ab[ ]+cv.lhu[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+1bc33eab[ ]+cv.lhu[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+1a5f3e2b[ ]+cv.lhu[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurr.s b/gas/testsuite/gas/riscv/cv-mem-lhurr.s
deleted file mode 100644
index 91511fd8dfd..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhurr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lhu t0, t1(t2)
- cv.lhu t4, t3(t1)
- cv.lhu t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
deleted file mode 100644
index 66e1a9019af..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+1263b2ab[ ]+cv.lhu[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+13c33eab[ ]+cv.lhu[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+125f3e2b[ ]+cv.lhu[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s b/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
deleted file mode 100644
index ff5d24ddc69..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lhu t0, (t2), t1
- cv.lhu t4, (t1), t3
- cv.lhu t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwpost.d b/gas/testsuite/gas/riscv/cv-mem-lwpost.d
deleted file mode 100644
index e0f1c58b102..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+8003a28b[ ]+cv.lw[ ]+t0,\(t2\),-2048
-[ ]+4:[ ]+00f32e8b[ ]+cv.lw[ ]+t4,\(t1\),15
-[ ]+8:[ ]+7fff2e0b[ ]+cv.lw[ ]+t3,\(t5\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwpost.s b/gas/testsuite/gas/riscv/cv-mem-lwpost.s
deleted file mode 100644
index 3942d64a465..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lw t0, (t2), -2048
- cv.lw t4, (t1), 15
- cv.lw t3, (t5), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrr.d b/gas/testsuite/gas/riscv/cv-mem-lwrr.d
deleted file mode 100644
index 8a72c021902..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0c63b2ab[ ]+cv.lw[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+0dc33eab[ ]+cv.lw[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+0c5f3e2b[ ]+cv.lw[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrr.s b/gas/testsuite/gas/riscv/cv-mem-lwrr.s
deleted file mode 100644
index 41be011bc36..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lw t0, t1(t2)
- cv.lw t4, t3(t1)
- cv.lw t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
deleted file mode 100644
index 502bd583d4e..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0463b2ab[ ]+cv.lw[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+05c33eab[ ]+cv.lw[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+045f3e2b[ ]+cv.lw[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s b/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
deleted file mode 100644
index 5dc9c230ff8..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.lw t0, (t2), t1
- cv.lw t4, (t1), t3
- cv.lw t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbpost.d b/gas/testsuite/gas/riscv/cv-mem-sbpost.d
deleted file mode 100644
index ba240958d6a..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+81f3002b[ ]+cv.sb[ ]+t6,\(t1\),-2048
-[ ]+4:[ ]+07d3822b[ ]+cv.sb[ ]+t4,\(t2\),100
-[ ]+8:[ ]+7fce8fab[ ]+cv.sb[ ]+t3,\(t4\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbpost.s b/gas/testsuite/gas/riscv/cv-mem-sbpost.s
deleted file mode 100644
index 1e3ff721468..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sb t6, (t1), -2048
- cv.sb t4, (t2), 100
- cv.sb t3, (t4), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrr.d b/gas/testsuite/gas/riscv/cv-mem-sbrr.d
deleted file mode 100644
index 806508957a5..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+2853b32b[ ]+cv.sb[ ]+t0,t1\(t2\)
-[ ]+4:[ ]+29d33e2b[ ]+cv.sb[ ]+t4,t3\(t1\)
-[ ]+8:[ ]+29cf32ab[ ]+cv.sb[ ]+t3,t0\(t5\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrr.s b/gas/testsuite/gas/riscv/cv-mem-sbrr.s
deleted file mode 100644
index b3a9e5269d9..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sb t0, t1(t2)
- cv.sb t4, t3(t1)
- cv.sb t3, t0(t5)
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
deleted file mode 100644
index 830e4e42c71..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+2053b32b[ ]+cv.sb[ ]+t0,\(t2\),t1
-[ ]+4:[ ]+21d33e2b[ ]+cv.sb[ ]+t4,\(t1\),t3
-[ ]+8:[ ]+21cf32ab[ ]+cv.sb[ ]+t3,\(t5\),t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s b/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
deleted file mode 100644
index f4813052e0d..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sb t0, (t2), t1
- cv.sb t4, (t1), t3
- cv.sb t3, (t5), t0
diff --git a/gas/testsuite/gas/riscv/cv-mem-shpost.d b/gas/testsuite/gas/riscv/cv-mem-shpost.d
deleted file mode 100644
index 2fc477518cd..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+81cf102b[ ]+cv.sh[ ]+t3,\(t5\),-2048
-[ ]+4:[ ]+026f9e2b[ ]+cv.sh[ ]+t1,\(t6\),60
-[ ]+8:[ ]+7e7e9fab[ ]+cv.sh[ ]+t2,\(t4\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-shpost.s b/gas/testsuite/gas/riscv/cv-mem-shpost.s
deleted file mode 100644
index d7ab1722d07..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sh t3, (t5), -2048
- cv.sh t1, (t6), 60
- cv.sh t2, (t4), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrr.d b/gas/testsuite/gas/riscv/cv-mem-shrr.d
deleted file mode 100644
index 0e88d9d320c..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+2a6ebe2b[ ]+cv.sh[ ]+t1,t3\(t4\)
-[ ]+4:[ ]+2bd333ab[ ]+cv.sh[ ]+t4,t2\(t1\)
-[ ]+8:[ ]+2bf3bf2b[ ]+cv.sh[ ]+t6,t5\(t2\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrr.s b/gas/testsuite/gas/riscv/cv-mem-shrr.s
deleted file mode 100644
index 2f5ee9859ac..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sh t1, t3(t4)
- cv.sh t4, t2(t1)
- cv.sh t6, t5(t2)
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrrpost.d b/gas/testsuite/gas/riscv/cv-mem-shrrpost.d
deleted file mode 100644
index f43ceddd64e..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+2263bfab[ ]+cv.sh[ ]+t1,\(t2\),t6
-[ ]+4:[ ]+22733f2b[ ]+cv.sh[ ]+t2,\(t1\),t5
-[ ]+8:[ ]+23ee3eab[ ]+cv.sh[ ]+t5,\(t3\),t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-shrrpost.s b/gas/testsuite/gas/riscv/cv-mem-shrrpost.s
deleted file mode 100644
index 922a94f7314..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-shrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sh t1, (t2), t6
- cv.sh t2, (t1), t5
- cv.sh t5, (t3), t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-swpost.d b/gas/testsuite/gas/riscv/cv-mem-swpost.d
deleted file mode 100644
index 2a5fee9833a..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+806ea02b[ ]+cv.sw[ ]+t1,\(t4\),-2048
-[ ]+4:[ ]+07cf222b[ ]+cv.sw[ ]+t3,\(t5\),100
-[ ]+8:[ ]+7e63afab[ ]+cv.sw[ ]+t1,\(t2\),2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-swpost.s b/gas/testsuite/gas/riscv/cv-mem-swpost.s
deleted file mode 100644
index 7dd827ac111..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sw t1, (t4), -2048
- cv.sw t3, (t5), 100
- cv.sw t1, (t2), 2047
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrr.d b/gas/testsuite/gas/riscv/cv-mem-swrr.d
deleted file mode 100644
index 5bc0708cbb8..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swrr.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+2c6eb3ab[ ]+cv.sw[ ]+t1,t2\(t4\)
-[ ]+4:[ ]+2dcf33ab[ ]+cv.sw[ ]+t3,t2\(t5\)
-[ ]+8:[ ]+2c63bf2b[ ]+cv.sw[ ]+t1,t5\(t2\)
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrr.s b/gas/testsuite/gas/riscv/cv-mem-swrr.s
deleted file mode 100644
index 652ac9a46f2..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swrr.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sw t1, t2(t4)
- cv.sw t3, t2(t5)
- cv.sw t1, t5(t2)
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrrpost.d b/gas/testsuite/gas/riscv/cv-mem-swrrpost.d
deleted file mode 100644
index d3b338563bd..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swrrpost.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_xcvmem
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+25e3bfab[ ]+cv.sw[ ]+t5,\(t2\),t6
-[ ]+4:[ ]+25ceb32b[ ]+cv.sw[ ]+t3,\(t4\),t1
-[ ]+8:[ ]+24733eab[ ]+cv.sw[ ]+t2,\(t1\),t4
diff --git a/gas/testsuite/gas/riscv/cv-mem-swrrpost.s b/gas/testsuite/gas/riscv/cv-mem-swrrpost.s
deleted file mode 100644
index 6210e1e2628..00000000000
--- a/gas/testsuite/gas/riscv/cv-mem-swrrpost.s
+++ /dev/null
@@ -1,4 +0,0 @@
-target:
- cv.sw t5, (t2), t6
- cv.sw t3, (t4), t1
- cv.sw t2, (t1), t4
diff --git a/gas/testsuite/gas/riscv/x-cv-alu-fail.d b/gas/testsuite/gas/riscv/x-cv-alu-fail.d
new file mode 100644
index 00000000000..2d1f1c9cf5b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-alu-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_xcvalu -I$srcdir/$subdir/
+#error_output: x-cv-alu-fail.l
diff --git a/gas/testsuite/gas/riscv/x-cv-alu-fail.l b/gas/testsuite/gas/riscv/x-cv-alu-fail.l
new file mode 100644
index 00000000000..b2fd8cc4690
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-alu-fail.l
@@ -0,0 +1,243 @@
+.*: Assembler messages:
+.*: unrecognized opcode `cv.abs t0,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.abs t3,t5', extension `xcvalu' required
+.*: unrecognized opcode `cv.addnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.addnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addn t0,t1,t2,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' required
+.*: unrecognized opcode `cv.addn t3,t5,t1,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrn t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' required
+.*: unrecognized opcode `cv.addrn t3,t6,t0,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.addunr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.addunr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addun t0,t1,t2,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' required
+.*: unrecognized opcode `cv.addun t3,t5,t1,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurn t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurn t6,t0,t3,14', extension `xcvalu' required
+.*: unrecognized opcode `cv.addurn t3,t6,t0,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipr t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipr t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.clip t0,t1,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' required
+.*: unrecognized opcode `cv.clip t3,t5,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipur t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipur t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipu t0,t1,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' required
+.*: unrecognized opcode `cv.clipu t3,t5,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbs t0,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbs t3,t5', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbz t0,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.extbz t3,t5', extension `xcvalu' required
+.*: unrecognized opcode `cv.exths t0,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.exths t3,t5', extension `xcvalu' required
+.*: unrecognized opcode `cv.exthz t0,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.exthz t3,t5', extension `xcvalu' required
+.*: unrecognized opcode `cv.max t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.max t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.maxu t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.maxu t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.min t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.min t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.minu t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.minu t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.sle t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.sle t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.sle t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.sleu t0,t1,t2', extension `xcvalu' required
+.*: unrecognized opcode `cv.sleu t4,t2,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.sleu t3,t5,t1', extension `xcvalu' required
+.*: unrecognized opcode `cv.subnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.subnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subn t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' required
+.*: unrecognized opcode `cv.subn t3,t6,t0,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrn t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' required
+.*: unrecognized opcode `cv.subrn t3,t6,t0,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.subunr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.subunr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subun t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' required
+.*: unrecognized opcode `cv.subun t3,t6,t0,31', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburnr t0,t3,t6', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburnr t3,t6,t0', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburn t0,t3,t6,0', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' required
+.*: unrecognized opcode `cv.suburn t3,t6,t0,31', extension `xcvalu' required
+.*: Error: illegal operands `cv.subnr 10,t3,t6'
+.*: Error: illegal operands `cv.addrnr t4,26,t6'
+.*: Error: illegal operands `cv.subunr t6,t3,15'
+.*: Error: instruction cv.clipu requires absolute expression
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: illegal operands `cv.clipu t0,t3,-10'
+.*: Error: illegal operands `cv.clipu t0,t3,500'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
+.*: Error: illegal operands `cv.addn t0,t3,t6,302'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
+.*: Error: illegal operands `cv.addn t0,t3,t6,32'
+.*: Error: illegal operands `cv.abs 5,t2'
+.*: Error: illegal operands `cv.slet 10,t2,t6'
+.*: Error: illegal operands `cv.sletu 11,t2,t6'
+.*: Error: illegal operands `cv.min 15,t2,t6'
+.*: Error: illegal operands `cv.minu 16,t2,t6'
+.*: Error: illegal operands `cv.max 8,t2,t6'
+.*: Error: illegal operands `cv.maxu 3,t2,t6'
+.*: Error: illegal operands `cv.exths 2,t2'
+.*: Error: illegal operands `cv.exthz 6,t2'
+.*: Error: illegal operands `cv.extbs 4,t2'
+.*: Error: illegal operands `cv.extbz 7,t2'
+.*: Error: illegal operands `cv.clip 17,t2,5'
+.*: Error: illegal operands `cv.clipu 11,t2,5'
+.*: Error: illegal operands `cv.clipr 16,t2,t6'
+.*: Error: illegal operands `cv.clipur 15,t2,t6'
+.*: Error: illegal operands `cv.addn 9,t2,t0,4'
+.*: Error: illegal operands `cv.addun 30,t2,t0,4'
+.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
+.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
+.*: Error: illegal operands `cv.addnr 2,t0,t3'
+.*: Error: illegal operands `cv.addunr 26,t0,t3'
+.*: Error: illegal operands `cv.addrnr 3,t0,t3'
+.*: Error: illegal operands `cv.addurnr 14,t0,t3'
+.*: Error: illegal operands `cv.subn 15,t0,t3,6'
+.*: Error: illegal operands `cv.subun 9,t0,t3,24'
+.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
+.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
+.*: Error: illegal operands `cv.subnr 3,t0,t3'
+.*: Error: illegal operands `cv.subunr 12,t0,t3'
+.*: Error: illegal operands `cv.subrnr 13,t0,t3'
+.*: Error: illegal operands `cv.suburnr 8,t0,t3'
+.*: Error: illegal operands `cv.abs t4,5'
+.*: Error: illegal operands `cv.slet t4,7,t6'
+.*: Error: illegal operands `cv.sletu t4,3,t6'
+.*: Error: illegal operands `cv.min t4,5,t6'
+.*: Error: illegal operands `cv.minu t4,3,t6'
+.*: Error: illegal operands `cv.max t4,4,t6'
+.*: Error: illegal operands `cv.maxu t4,6,t6'
+.*: Error: illegal operands `cv.exths t4,30'
+.*: Error: illegal operands `cv.exthz t4,23'
+.*: Error: illegal operands `cv.extbs t4,25'
+.*: Error: illegal operands `cv.extbz t4,21'
+.*: Error: illegal operands `cv.clip t4,2,5'
+.*: Error: illegal operands `cv.clipu t4,16,5'
+.*: Error: illegal operands `cv.clipr t4,17,t6'
+.*: Error: illegal operands `cv.clipur t4,14,t6'
+.*: Error: illegal operands `cv.addn t4,5,t0,4'
+.*: Error: illegal operands `cv.addun t4,18,t0,4'
+.*: Error: illegal operands `cv.addrn t6,19,t3,9'
+.*: Error: illegal operands `cv.addurn t6,4,t3,14'
+.*: Error: illegal operands `cv.addnr t6,6,t3'
+.*: Error: illegal operands `cv.addunr t6,7,t3'
+.*: Error: illegal operands `cv.addrnr t6,9,t3'
+.*: Error: illegal operands `cv.addurnr t6,5,t3'
+.*: Error: illegal operands `cv.subn t6,11,t3,6'
+.*: Error: illegal operands `cv.subun t6,14,t3,24'
+.*: Error: illegal operands `cv.subrn t6,15,t3,21'
+.*: Error: illegal operands `cv.suburn t6,24,t3,3'
+.*: Error: illegal operands `cv.subnr t6,4,t3'
+.*: Error: illegal operands `cv.subunr t6,8,t3'
+.*: Error: illegal operands `cv.subrnr t6,7,t3'
+.*: Error: illegal operands `cv.suburnr t6,6,t3'
+.*: Error: illegal operands `cv.slet t4,t2,3'
+.*: Error: illegal operands `cv.sletu t4,t2,4'
+.*: Error: illegal operands `cv.min t4,t2,13'
+.*: Error: illegal operands `cv.minu t4,t2,7'
+.*: Error: illegal operands `cv.max t4,t2,17'
+.*: Error: illegal operands `cv.maxu t4,t2,30'
+.*: Error: illegal operands `cv.clipr t4,t2,18'
+.*: Error: illegal operands `cv.clipur t4,t2,29'
+.*: Error: illegal operands `cv.addn t4,t2,24,4'
+.*: Error: illegal operands `cv.addun t4,t2,6,4'
+.*: Error: illegal operands `cv.addrn t6,t0,7,9'
+.*: Error: illegal operands `cv.addurn t6,t0,18,14'
+.*: Error: illegal operands `cv.addnr t6,t0,15'
+.*: Error: illegal operands `cv.addunr t6,t0,24'
+.*: Error: illegal operands `cv.addrnr t6,t0,3'
+.*: Error: illegal operands `cv.addurnr t6,t0,2'
+.*: Error: illegal operands `cv.subn t6,t0,1,6'
+.*: Error: illegal operands `cv.subun t6,t0,8,24'
+.*: Error: illegal operands `cv.subrn t6,t0,18,21'
+.*: Error: illegal operands `cv.suburn t6,t0,25,3'
+.*: Error: illegal operands `cv.subnr t6,t0,14'
+.*: Error: illegal operands `cv.subunr t6,t0,7'
+.*: Error: illegal operands `cv.subrnr t6,t0,18'
+.*: Error: illegal operands `cv.suburnr t6,t0,26'
+.*: Error: instruction cv.clip requires absolute expression
+.*: Error: instruction cv.clipu requires absolute expression
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: instruction cv.addun requires absolute expression
+.*: Error: instruction cv.addrn requires absolute expression
+.*: Error: instruction cv.addurn requires absolute expression
+.*: Error: instruction cv.subn requires absolute expression
+.*: Error: instruction cv.subun requires absolute expression
+.*: Error: instruction cv.subrn requires absolute expression
+.*: Error: instruction cv.suburn requires absolute expression
+.*: Error: illegal operands `cv.clip t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clip t0,t3,-400'
+.*: Error: illegal operands `cv.clipu t0,t3,-985'
+.*: Error: illegal operands `cv.clip t0,t3,32'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.clip t0,t3,859'
+.*: Error: illegal operands `cv.clipu t0,t3,7283'
+.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
+.*: Error: illegal operands `cv.addn t4,t2,t0,32'
+.*: Error: illegal operands `cv.addun t4,t2,t0,32'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subun t6,t0,t3,32'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addn t4,t2,t0,320'
+.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
+.*: Error: illegal operands `cv.subn t6,t0,t3,89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
diff --git a/gas/testsuite/gas/riscv/x-cv-alu-fail.s b/gas/testsuite/gas/riscv/x-cv-alu-fail.s
new file mode 100644
index 00000000000..4dfc9eeacd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-alu-fail.s
@@ -0,0 +1,170 @@
+ # xcvalu - architecture set
+ .option push
+ .option arch, rv32i
+ .include "x-cv-alu.s"
+ .option pop
+
+ # xcvalu - boundaries
+ cv.subnr 10, t3, t6 # Destination must be of type register
+ cv.addrnr t4, 26, t6 # Source 1 must be of type register
+ cv.subunr t6, t3, 15 # Source 2 must be of type register
+ cv.clipu t0, t3, t6 # Five bit immediate must be an absolute value
+ cv.addn t0, t3, t6, t2 # Five bit immediate must be an absolute value
+ cv.clipu t0, t3, -10 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 500 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -60 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 302 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -1 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 32 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -1 # Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 32 # Five bit immediate must be an absolute value in range [0, 31]
+
+ # xcvalu - destination must be of type register
+ cv.abs 5,t2
+ cv.slet 10,t2,t6
+ cv.sletu 11,t2,t6
+ cv.min 15,t2,t6
+ cv.minu 16,t2,t6
+ cv.max 8,t2,t6
+ cv.maxu 3,t2,t6
+ cv.exths 2,t2
+ cv.exthz 6,t2
+ cv.extbs 4,t2
+ cv.extbz 7,t2
+ cv.clip 17,t2,5
+ cv.clipu 11,t2,5
+ cv.clipr 16,t2,t6
+ cv.clipur 15,t2,t6
+ cv.addn 9,t2,t0,4
+ cv.addun 30,t2,t0,4
+ cv.addrn 21,t0,t3,9
+ cv.addurn 6,t0,t3,14
+ cv.addnr 2,t0,t3
+ cv.addunr 26,t0,t3
+ cv.addrnr 3,t0,t3
+ cv.addurnr 14,t0,t3
+ cv.subn 15,t0,t3,6
+ cv.subun 9,t0,t3,24
+ cv.subrn 24,t0,t3,21
+ cv.suburn 25,t0,t3,3
+ cv.subnr 3,t0,t3
+ cv.subunr 12,t0,t3
+ cv.subrnr 13,t0,t3
+ cv.suburnr 8,t0,t3
+
+ # xcvalu - source 1 must be of type register
+ cv.abs t4,5
+ cv.slet t4,7,t6
+ cv.sletu t4,3,t6
+ cv.min t4,5,t6
+ cv.minu t4,3,t6
+ cv.max t4,4,t6
+ cv.maxu t4,6,t6
+ cv.exths t4,30
+ cv.exthz t4,23
+ cv.extbs t4,25
+ cv.extbz t4,21
+ cv.clip t4,2,5
+ cv.clipu t4,16,5
+ cv.clipr t4,17,t6
+ cv.clipur t4,14,t6
+ cv.addn t4,5,t0,4
+ cv.addun t4,18,t0,4
+ cv.addrn t6,19,t3,9
+ cv.addurn t6,4,t3,14
+ cv.addnr t6,6,t3
+ cv.addunr t6,7,t3
+ cv.addrnr t6,9,t3
+ cv.addurnr t6,5,t3
+ cv.subn t6,11,t3,6
+ cv.subun t6,14,t3,24
+ cv.subrn t6,15,t3,21
+ cv.suburn t6,24,t3,3
+ cv.subnr t6,4,t3
+ cv.subunr t6,8,t3
+ cv.subrnr t6,7,t3
+ cv.suburnr t6,6,t3
+
+ # xcvalu - source 2 must be of type register
+ cv.slet t4,t2,3
+ cv.sletu t4,t2,4
+ cv.min t4,t2,13
+ cv.minu t4,t2,7
+ cv.max t4,t2,17
+ cv.maxu t4,t2,30
+ cv.clipr t4,t2,18
+ cv.clipur t4,t2,29
+ cv.addn t4,t2,24,4
+ cv.addun t4,t2,6,4
+ cv.addrn t6,t0,7,9
+ cv.addurn t6,t0,18,14
+ cv.addnr t6,t0,15
+ cv.addunr t6,t0,24
+ cv.addrnr t6,t0,3
+ cv.addurnr t6,t0,2
+ cv.subn t6,t0,1,6
+ cv.subun t6,t0,8,24
+ cv.subrn t6,t0,18,21
+ cv.suburn t6,t0,25,3
+ cv.subnr t6,t0,14
+ cv.subunr t6,t0,7
+ cv.subrnr t6,t0,18
+ cv.suburnr t6,t0,26
+
+ # xcvalu - five bit immediate must be an absolute value
+ cv.clip t4,t2,t3
+ cv.clipu t4,t2,t3
+
+ # xcvalu - five bit immediate must be an absolute value
+ cv.addn t4,t2,t0,t3
+ cv.addun t4,t2,t0,t3
+ cv.addrn t6,t0,t3,t2
+ cv.addurn t6,t0,t3,t2
+ cv.subn t6,t0,t3,t2
+ cv.subun t6,t0,t3,t2
+ cv.subrn t6,t0,t3,t2
+ cv.suburn t6,t0,t3,t2
+
+ # xcvalu - five bit immediate must be an absolute value in range [0, 31]
+ cv.clip t0,t3,-1
+ cv.clipu t0,t3,-1
+ cv.clip t0,t3,-400
+ cv.clipu t0,t3,-985
+ cv.clip t0,t3,32
+ cv.clipu t0,t3,32
+ cv.clip t0,t3,859
+ cv.clipu t0,t3,7283
+
+ # xcvalu - five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t4,t2,t0,-1
+ cv.addun t4,t2,t0,-1
+ cv.addrn t6,t0,t3,-1
+ cv.addurn t6,t0,t3,-1
+ cv.subn t6,t0,t3,-1
+ cv.subun t6,t0,t3,-1
+ cv.subrn t6,t0,t3,-1
+ cv.suburn t6,t0,t3,-1
+ cv.addn t4,t2,t0,-34
+ cv.addun t4,t2,t0,-3556
+ cv.addrn t6,t0,t3,-212
+ cv.addurn t6,t0,t3,-6584
+ cv.subn t6,t0,t3,-89
+ cv.subun t6,t0,t3,-9034
+ cv.subrn t6,t0,t3,-234
+ cv.suburn t6,t0,t3,-284
+ cv.addn t4,t2,t0,32
+ cv.addun t4,t2,t0,32
+ cv.addrn t6,t0,t3,32
+ cv.addurn t6,t0,t3,32
+ cv.subn t6,t0,t3,32
+ cv.subun t6,t0,t3,32
+ cv.subrn t6,t0,t3,32
+ cv.suburn t6,t0,t3,32
+ cv.addn t4,t2,t0,320
+ cv.addun t4,t2,t0,34534
+ cv.addrn t6,t0,t3,254
+ cv.addurn t6,t0,t3,398
+ cv.subn t6,t0,t3,89
+ cv.subun t6,t0,t3,3489
+ cv.subrn t6,t0,t3,143
+ cv.suburn t6,t0,t3,234
diff --git a/gas/testsuite/gas/riscv/x-cv-alu.d b/gas/testsuite/gas/riscv/x-cv-alu.d
new file mode 100644
index 00000000000..81f841e568f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-alu.d
@@ -0,0 +1,102 @@
+#as: -march=rv32i_xcvalu
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <.text>:
+[ ]+[0-9a-f]+:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
+[ ]+[0-9a-f]+:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
+[ ]+[0-9a-f]+:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
+[ ]+[0-9a-f]+:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
+[ ]+[0-9a-f]+:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
+[ ]+[0-9a-f]+:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
+[ ]+[0-9a-f]+:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
+[ ]+[0-9a-f]+:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
+[ ]+[0-9a-f]+:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
+[ ]+[0-9a-f]+:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
+[ ]+[0-9a-f]+:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
+[ ]+[0-9a-f]+:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
+[ ]+[0-9a-f]+:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
+[ ]+[0-9a-f]+:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
+[ ]+[0-9a-f]+:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
+[ ]+[0-9a-f]+:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
+[ ]+[0-9a-f]+:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
+[ ]+[0-9a-f]+:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
+[ ]+[0-9a-f]+:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
+[ ]+[0-9a-f]+:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
+[ ]+[0-9a-f]+:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
+[ ]+[0-9a-f]+:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
+[ ]+[0-9a-f]+:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
+[ ]+[0-9a-f]+:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
+[ ]+[0-9a-f]+:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
+[ ]+[0-9a-f]+:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
+[ ]+[0-9a-f]+:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
+[ ]+[0-9a-f]+:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
+[ ]+[0-9a-f]+:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
+[ ]+[0-9a-f]+:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
+[ ]+[0-9a-f]+:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
+[ ]+[0-9a-f]+:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
+[ ]+[0-9a-f]+:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
+[ ]+[0-9a-f]+:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
+[ ]+[0-9a-f]+:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s b/gas/testsuite/gas/riscv/x-cv-alu.s
similarity index 99%
rename from gas/testsuite/gas/riscv/cv-alu-insns.s
rename to gas/testsuite/gas/riscv/x-cv-alu.s
index 82ea0c3b98d..608c4cee01e 100644
--- a/gas/testsuite/gas/riscv/cv-alu-insns.s
+++ b/gas/testsuite/gas/riscv/x-cv-alu.s
@@ -1,4 +1,3 @@
-target:
cv.abs t0,t1
cv.abs t4,t2
cv.abs t3,t5
diff --git a/gas/testsuite/gas/riscv/x-cv-bi-fail.d b/gas/testsuite/gas/riscv/x-cv-bi-fail.d
new file mode 100644
index 00000000000..525908f424c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bi-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_xcvbi -I$srcdir/$subdir/
+#error_output: x-cv-bi-fail.l
diff --git a/gas/testsuite/gas/riscv/x-cv-bi-fail.l b/gas/testsuite/gas/riscv/x-cv-bi-fail.l
new file mode 100644
index 00000000000..92fdcb0501a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bi-fail.l
@@ -0,0 +1,19 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.beqimm t0,-16,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.beqimm t4,5,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.beqimm t2,15,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.bneimm t0,-16,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.bneimm t4,5,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.bneimm t2,15,foo', extension `xcvbi' required
+.*: Error: illegal operands `cv.beqimm 20,10,foo'
+.*: Error: illegal operands `cv.bneimm 8,-4,foo'
+.*: Error: instruction cv.beqimm requires absolute expression
+.*: Error: instruction cv.bneimm requires absolute expression
+.*: Error: illegal operands `cv.beqimm t0,-17,foo'
+.*: Error: illegal operands `cv.beqimm t2,-32,foo'
+.*: Error: illegal operands `cv.beqimm t4,16,foo'
+.*: Error: illegal operands `cv.beqimm t3,44,foo'
+.*: Error: illegal operands `cv.bneimm t0,-17,foo'
+.*: Error: illegal operands `cv.bneimm t2,-32,foo'
+.*: Error: illegal operands `cv.bneimm t4,16,foo'
+.*: Error: illegal operands `cv.bneimm t3,44,foo'
diff --git a/gas/testsuite/gas/riscv/x-cv-bi-fail.s b/gas/testsuite/gas/riscv/x-cv-bi-fail.s
new file mode 100644
index 00000000000..4be7760f0ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bi-fail.s
@@ -0,0 +1,24 @@
+ # xcvbi - architecture set
+ .option push
+ .option arch, rv32i
+ .include "x-cv-bi.s"
+ .option pop
+
+foo:
+ # xcvbi - comparison target must be a register
+ cv.beqimm 20, 10, foo
+ cv.bneimm 8, -4, foo
+
+ # xcvbi - comparison value must be an immediate
+ cv.beqimm t0, t1, foo
+ cv.bneimm t3, t4, foo
+
+ # xcvbi - comparison value must be an immediate in range [-16, +15]
+ cv.beqimm t0, -17, foo
+ cv.beqimm t2, -32, foo
+ cv.beqimm t4, 16, foo
+ cv.beqimm t3, 44, foo
+ cv.bneimm t0, -17, foo
+ cv.bneimm t2, -32, foo
+ cv.bneimm t4, 16, foo
+ cv.bneimm t3, 44, foo
diff --git a/gas/testsuite/gas/riscv/x-cv-bi.d b/gas/testsuite/gas/riscv/x-cv-bi.d
new file mode 100644
index 00000000000..76b7e738496
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bi.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ ]+[0-9a-f]+:[ ]+0102e00b[ ]+cv.beqimm[ ]+t0,-16,0[ ]+<foo>
+[ ]+[0-9a-f]+:[ ]+fe5eee8b[ ]+cv.beqimm[ ]+t4,5,0[ ]+<foo>
+[ ]+[0-9a-f]+:[ ]+fef3ec8b[ ]+cv.beqimm[ ]+t2,15,0[ ]+<foo>
+[ ]+[0-9a-f]+:[ ]+ff02fa8b[ ]+cv.bneimm[ ]+t0,-16,0[ ]+<foo>
+[ ]+[0-9a-f]+:[ ]+fe5ef88b[ ]+cv.bneimm[ ]+t4,5,0[ ]+<foo>
+[ ]+[0-9a-f]+:[ ]+fef3f68b[ ]+cv.bneimm[ ]+t2,15,0[ ]+<foo>
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.s b/gas/testsuite/gas/riscv/x-cv-bi.s
similarity index 51%
rename from gas/testsuite/gas/riscv/cv-bi-beqimm.s
rename to gas/testsuite/gas/riscv/x-cv-bi.s
index 7fbb8f27515..9c06babd0ce 100644
--- a/gas/testsuite/gas/riscv/cv-bi-beqimm.s
+++ b/gas/testsuite/gas/riscv/x-cv-bi.s
@@ -2,3 +2,6 @@ foo:
cv.beqimm t0, -16, foo
cv.beqimm t4, 5, foo
cv.beqimm t2, 15, foo
+ cv.bneimm t0, -16, foo
+ cv.bneimm t4, 5, foo
+ cv.bneimm t2, 15, foo
diff --git a/gas/testsuite/gas/riscv/x-cv-elw-fail.d b/gas/testsuite/gas/riscv/x-cv-elw-fail.d
new file mode 100644
index 00000000000..db1d7ff86d2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-elw-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_xcvelw -I$srcdir/$subdir/
+#error_output: x-cv-elw-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.l b/gas/testsuite/gas/riscv/x-cv-elw-fail.l
similarity index 93%
rename from gas/testsuite/gas/riscv/cv-elw-fail-march.l
rename to gas/testsuite/gas/riscv/x-cv-elw-fail.l
index 760a71b3827..2e8a65b28ae 100644
--- a/gas/testsuite/gas/riscv/cv-elw-fail-march.l
+++ b/gas/testsuite/gas/riscv/x-cv-elw-fail.l
@@ -36,3 +36,7 @@
.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension `xcvelw' required
.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension `xcvelw' required
.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension `xcvelw' required
+.*: Error: illegal operands `cv.elw x5,-2049\(x6\)'
+.*: Error: illegal operands `cv.elw x5,2048\(x6\)'
+.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)'
+.*: Error: illegal operands `cv.elw x32,1024\(x32\)'
diff --git a/gas/testsuite/gas/riscv/x-cv-elw-fail.s b/gas/testsuite/gas/riscv/x-cv-elw-fail.s
new file mode 100644
index 00000000000..8c92e05a68b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-elw-fail.s
@@ -0,0 +1,13 @@
+ # xcvelw - architecture set
+ .option push
+ .option arch, rv32i
+ .include "x-cv-elw.s"
+ .option pop
+
+ # xcvelw - immediate Boundary Tests
+ cv.elw x5,-2049(x6)
+ cv.elw x5,2048(x6)
+
+ # xcvelw - register Boundary Tests
+ cv.elw x-1,1024(x-1)
+ cv.elw x32,1024(x32)
diff --git a/gas/testsuite/gas/riscv/x-cv-elw.d b/gas/testsuite/gas/riscv/x-cv-elw.d
new file mode 100644
index 00000000000..845be657518
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-elw.d
@@ -0,0 +1,45 @@
+#as: -march=rv32i_xcvelw
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+8003628b[ ]+cv.elw[ ]+t0,-2048\(t1\)
+[ ]+[0-9a-f]+:[ ]+0003628b[ ]+cv.elw[ ]+t0,0\(t1\)
+[ ]+[0-9a-f]+:[ ]+0143628b[ ]+cv.elw[ ]+t0,20\(t1\)
+[ ]+[0-9a-f]+:[ ]+7ff3628b[ ]+cv.elw[ ]+t0,2047\(t1\)
+[ ]+[0-9a-f]+:[ ]+7fffef8b[ ]+cv.elw[ ]+t6,2047\(t6\)
+[ ]+[0-9a-f]+:[ ]+0000600b[ ]+cv.elw[ ]+zero,0\(zero\) # 0 <.text>
+[ ]+[0-9a-f]+:[ ]+4000e08b[ ]+cv.elw[ ]+ra,1024\(ra\)
+[ ]+[0-9a-f]+:[ ]+4001610b[ ]+cv.elw[ ]+sp,1024\(sp\)
+[ ]+[0-9a-f]+:[ ]+4001e18b[ ]+cv.elw[ ]+gp,1024\(gp\)
+[ ]+[0-9a-f]+:[ ]+4002620b[ ]+cv.elw[ ]+tp,1024\(tp\) # 400 <.text\+0x400>
+[ ]+[0-9a-f]+:[ ]+4002e28b[ ]+cv.elw[ ]+t0,1024\(t0\)
+[ ]+[0-9a-f]+:[ ]+4003630b[ ]+cv.elw[ ]+t1,1024\(t1\)
+[ ]+[0-9a-f]+:[ ]+4003e38b[ ]+cv.elw[ ]+t2,1024\(t2\)
+[ ]+[0-9a-f]+:[ ]+4004640b[ ]+cv.elw[ ]+s0,1024\(s0\)
+[ ]+[0-9a-f]+:[ ]+4004e48b[ ]+cv.elw[ ]+s1,1024\(s1\)
+[ ]+[0-9a-f]+:[ ]+4005650b[ ]+cv.elw[ ]+a0,1024\(a0\)
+[ ]+[0-9a-f]+:[ ]+4005e58b[ ]+cv.elw[ ]+a1,1024\(a1\)
+[ ]+[0-9a-f]+:[ ]+4006660b[ ]+cv.elw[ ]+a2,1024\(a2\)
+[ ]+[0-9a-f]+:[ ]+4006e68b[ ]+cv.elw[ ]+a3,1024\(a3\)
+[ ]+[0-9a-f]+:[ ]+4007670b[ ]+cv.elw[ ]+a4,1024\(a4\)
+[ ]+[0-9a-f]+:[ ]+4007e78b[ ]+cv.elw[ ]+a5,1024\(a5\)
+[ ]+[0-9a-f]+:[ ]+4008680b[ ]+cv.elw[ ]+a6,1024\(a6\)
+[ ]+[0-9a-f]+:[ ]+4008e88b[ ]+cv.elw[ ]+a7,1024\(a7\)
+[ ]+[0-9a-f]+:[ ]+4009690b[ ]+cv.elw[ ]+s2,1024\(s2\)
+[ ]+[0-9a-f]+:[ ]+4009e98b[ ]+cv.elw[ ]+s3,1024\(s3\)
+[ ]+[0-9a-f]+:[ ]+400a6a0b[ ]+cv.elw[ ]+s4,1024\(s4\)
+[ ]+[0-9a-f]+:[ ]+400aea8b[ ]+cv.elw[ ]+s5,1024\(s5\)
+[ ]+[0-9a-f]+:[ ]+400b6b0b[ ]+cv.elw[ ]+s6,1024\(s6\)
+[ ]+[0-9a-f]+:[ ]+400beb8b[ ]+cv.elw[ ]+s7,1024\(s7\)
+[ ]+[0-9a-f]+:[ ]+400c6c0b[ ]+cv.elw[ ]+s8,1024\(s8\)
+[ ]+[0-9a-f]+:[ ]+400cec8b[ ]+cv.elw[ ]+s9,1024\(s9\)
+[ ]+[0-9a-f]+:[ ]+400d6d0b[ ]+cv.elw[ ]+s10,1024\(s10\)
+[ ]+[0-9a-f]+:[ ]+400ded8b[ ]+cv.elw[ ]+s11,1024\(s11\)
+[ ]+[0-9a-f]+:[ ]+400e6e0b[ ]+cv.elw[ ]+t3,1024\(t3\)
+[ ]+[0-9a-f]+:[ ]+400eee8b[ ]+cv.elw[ ]+t4,1024\(t4\)
+[ ]+[0-9a-f]+:[ ]+400f6f0b[ ]+cv.elw[ ]+t5,1024\(t5\)
+[ ]+[0-9a-f]+:[ ]+400fef8b[ ]+cv.elw[ ]+t6,1024\(t6\)
diff --git a/gas/testsuite/gas/riscv/x-cv-elw.s b/gas/testsuite/gas/riscv/x-cv-elw.s
new file mode 100644
index 00000000000..3d67060268b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-elw.s
@@ -0,0 +1,40 @@
+ # Immediate Boundary Tests
+ cv.elw x5,-2048(x6)
+ cv.elw x5,0(x6)
+ cv.elw x5,20(x6)
+ cv.elw x5,2047(x6)
+ cv.elw x31,2047(x31)
+
+ # Register Boundary Tests
+ cv.elw x0,0(x0)
+ cv.elw x1,1024(x1)
+ cv.elw x2,1024(x2)
+ cv.elw x3,1024(x3)
+ cv.elw x4,1024(x4)
+ cv.elw x5,1024(x5)
+ cv.elw x6,1024(x6)
+ cv.elw x7,1024(x7)
+ cv.elw x8,1024(x8)
+ cv.elw x9,1024(x9)
+ cv.elw x10,1024(x10)
+ cv.elw x11,1024(x11)
+ cv.elw x12,1024(x12)
+ cv.elw x13,1024(x13)
+ cv.elw x14,1024(x14)
+ cv.elw x15,1024(x15)
+ cv.elw x16,1024(x16)
+ cv.elw x17,1024(x17)
+ cv.elw x18,1024(x18)
+ cv.elw x19,1024(x19)
+ cv.elw x20,1024(x20)
+ cv.elw x21,1024(x21)
+ cv.elw x22,1024(x22)
+ cv.elw x23,1024(x23)
+ cv.elw x24,1024(x24)
+ cv.elw x25,1024(x25)
+ cv.elw x26,1024(x26)
+ cv.elw x27,1024(x27)
+ cv.elw x28,1024(x28)
+ cv.elw x29,1024(x29)
+ cv.elw x30,1024(x30)
+ cv.elw x31,1024(x31)
diff --git a/gas/testsuite/gas/riscv/x-cv-mac-fail.d b/gas/testsuite/gas/riscv/x-cv-mac-fail.d
new file mode 100644
index 00000000000..b9e13fba651
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mac-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_xcvmac -I$srcdir/$subdir/
+#error_output: x-cv-mac-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l b/gas/testsuite/gas/riscv/x-cv-mac-fail.l
similarity index 54%
rename from gas/testsuite/gas/riscv/cv-mac-fail-operand.l
rename to gas/testsuite/gas/riscv/x-cv-mac-fail.l
index 645949696cb..a72d1382e4d 100644
--- a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
+++ b/gas/testsuite/gas/riscv/x-cv-mac-fail.l
@@ -1,4 +1,82 @@
.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.mac t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mac t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t0,t1,t2', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t3,t5,t1', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t3,t5,t1,31', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t3,t5,t1,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t3,t5,t1,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t3,t5,t1,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t0,t1,t2,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t3,t5,t1,0', extension `xcvmac' required
.*: Error: illegal operands `cv.mac 8,t2,t0'
.*: Error: illegal operands `cv.msu 23,t2,t0'
.*: Error: illegal operands `cv.muls 43,t2,t0'
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s b/gas/testsuite/gas/riscv/x-cv-mac-fail.s
similarity index 91%
rename from gas/testsuite/gas/riscv/cv-mac-fail-operand.s
rename to gas/testsuite/gas/riscv/x-cv-mac-fail.s
index 97a29448ebd..92f935dfc4a 100644
--- a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
+++ b/gas/testsuite/gas/riscv/x-cv-mac-fail.s
@@ -1,5 +1,10 @@
-# Destination must be of type register
-target:
+ # xcvmac - architecture set
+ .option push
+ .option arch, rv32i
+ .include "x-cv-mac.s"
+ .option pop
+
+ # xcvmac - destination must be of type register
cv.mac 8, t2, t0
cv.msu 23, t2, t0
cv.muls 43, t2, t0
@@ -23,7 +28,7 @@ target:
cv.macurn 35, t2, t0, 25
cv.machhurn 67, t2, t0, 5
-# Source one must be of type register
+ # xcvmac - source one must be of type register
cv.mac t4, 43, t0
cv.msu t4, 3, t0
cv.muls t4, 345, t0
@@ -47,7 +52,7 @@ target:
cv.macurn t4, 49, t0, 25
cv.machhurn t4, 6, t0, 5
-# Source two must be of type register
+ # xcvmac - source two must be of type register
cv.mac t4, t2, 344
cv.msu t4, t2, 23
cv.muls t4, t2, 2
@@ -71,7 +76,7 @@ target:
cv.macurn t4, t2, 900, 25
cv.machhurn t4, t2, 354, 5
-# Immediate value must be in range [0, 31]
+ # xcvmac - immediate value must be in range [0, 31]
cv.mulsn t4, t2, t0, -1
cv.mulhhsn t4, t2, t0, -1
cv.mulsrn t4, t2, t0, -1
@@ -136,7 +141,7 @@ target:
cv.machhun t4, t2, t0, 1245
cv.macurn t4, t2, t0, 45
-# Immediate value must be an absolute expression
+ # xcvmac - immediate value must be an absolute expression
cv.mulsn t4, t2, t0, t3
cv.mulhhsn t4, t2, t0, t1
cv.mulsrn t4, t2, t0, t6
diff --git a/gas/testsuite/gas/riscv/x-cv-mac.d b/gas/testsuite/gas/riscv/x-cv-mac.d
new file mode 100644
index 00000000000..d13623227c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mac.d
@@ -0,0 +1,87 @@
+#as: -march=rv32i_xcvmac
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
+[ ]+[0-9a-f]+:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
+[ ]+[0-9a-f]+:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
+[ ]+[0-9a-f]+:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
+[ ]+[0-9a-f]+:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
+[ ]+[0-9a-f]+:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
+[ ]+[0-9a-f]+:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
+[ ]+[0-9a-f]+:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
+[ ]+[0-9a-f]+:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
+[ ]+[0-9a-f]+:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
+[ ]+[0-9a-f]+:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
+[ ]+[0-9a-f]+:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
+[ ]+[0-9a-f]+:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
+[ ]+[0-9a-f]+:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
+[ ]+[0-9a-f]+:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
+[ ]+[0-9a-f]+:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
+[ ]+[0-9a-f]+:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
+[ ]+[0-9a-f]+:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
+[ ]+[0-9a-f]+:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
+[ ]+[0-9a-f]+:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
+[ ]+[0-9a-f]+:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
+[ ]+[0-9a-f]+:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+[0-9a-f]+:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+[0-9a-f]+:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+[0-9a-f]+:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.s b/gas/testsuite/gas/riscv/x-cv-mac.s
similarity index 98%
rename from gas/testsuite/gas/riscv/cv-mac-insns.s
rename to gas/testsuite/gas/riscv/x-cv-mac.s
index a699a3ba461..c3a26f294f3 100644
--- a/gas/testsuite/gas/riscv/cv-mac-insns.s
+++ b/gas/testsuite/gas/riscv/x-cv-mac.s
@@ -1,4 +1,3 @@
-target:
cv.mac t0, t1, t2
cv.mac t4, t2, t0
cv.mac t3, t5, t1
@@ -66,7 +65,7 @@ target:
cv.mulurn t4, t2, t0, 11
cv.mulurn t3, t5, t1, 31
- # Pseudo-instructions
+ # Pseudo-instructions
cv.mulhhsn t0, t1, t2, 0
cv.mulhhsn t4, t2, t0, 0
cv.mulhhsn t3, t5, t1, 0
diff --git a/gas/testsuite/gas/riscv/x-cv-mem-fail.d b/gas/testsuite/gas/riscv/x-cv-mem-fail.d
new file mode 100644
index 00000000000..11c80be3c6e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mem-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_xcvmem -I$srcdir/$subdir/
+#error_output: x-cv-mem-fail.l
diff --git a/gas/testsuite/gas/riscv/x-cv-mem-fail.l b/gas/testsuite/gas/riscv/x-cv-mem-fail.l
new file mode 100644
index 00000000000..f23dc600348
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mem-fail.l
@@ -0,0 +1,201 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.lb t0,\(t2\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t4,\(t1\),15', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t3,\(t5\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lb t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t0,\(t2\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t4,\(t1\),15', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t3,\(t5\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lbu t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t0,\(t2\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t4,\(t1\),15', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t3,\(t5\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lh t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,\(t2\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t4,\(t1\),15', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t3,\(t5\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lhu t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t0,\(t2\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t4,\(t1\),15', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t3,\(t5\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.lw t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t6,\(t1\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t4,\(t2\),100', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t3,\(t4\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t0,t1\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t4,t3\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t3,t0\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t0,\(t2\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t4,\(t1\),t3', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sb t3,\(t5\),t0', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t3,\(t5\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t1,\(t6\),60', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t2,\(t4\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t1,t3\(t4\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t4,t2\(t1\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t6,t5\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t1,\(t2\),t6', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t2,\(t1\),t5', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sh t5,\(t3\),t4', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,\(t4\),-2048', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t3,\(t5\),100', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,\(t2\),2047', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,t2\(t4\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t3,t2\(t5\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t1,t5\(t2\)', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t5,\(t2\),t6', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t3,\(t4\),t1', extension `xcvmem' required
+.*: Error: unrecognized opcode `cv.sw t2,\(t1\),t4', extension `xcvmem' required
+.*: Error: illegal operands `cv.lb 20,10\(t1\)'
+.*: Error: illegal operands `cv.lb 32,\(t2\),15'
+.*: Error: illegal operands `cv.lb 40,t2\(t3\)'
+.*: Error: illegal operands `cv.lb 28,\(t4\),t3'
+.*: Error: illegal operands `cv.lbu 16,20\(t5\)'
+.*: Error: illegal operands `cv.lbu 20,\(t6\),30'
+.*: Error: illegal operands `cv.lbu 44,t4\(t1\)'
+.*: Error: illegal operands `cv.lbu 48,\(t2\),t5'
+.*: Error: illegal operands `cv.lh 52,25\(t3\)'
+.*: Error: illegal operands `cv.lh 12,\(t4\),10'
+.*: Error: illegal operands `cv.lh 16,t6\(t5\)'
+.*: Error: illegal operands `cv.lh 36,\(t6\),t1'
+.*: Error: illegal operands `cv.lhu 24,35\(t1\)'
+.*: Error: illegal operands `cv.lhu 12,\(t2\),13'
+.*: Error: illegal operands `cv.lhu 32,t2\(t3\)'
+.*: Error: illegal operands `cv.lhu 40,\(t4\),t3'
+.*: Error: illegal operands `cv.lw 44,18\(t5\)'
+.*: Error: illegal operands `cv.lw 48,\(t6\),8'
+.*: Error: illegal operands `cv.lw 24,t4\(t1\)'
+.*: Error: illegal operands `cv.lw 12,\(t2\),t5'
+.*: Error: illegal operands `cv.sb 12,10\(t1\)'
+.*: Error: illegal operands `cv.sb 14,\(t2\),20'
+.*: Error: illegal operands `cv.sb 16,t1\(t3\)'
+.*: Error: illegal operands `cv.sb 20,\(t4\),t2'
+.*: Error: illegal operands `cv.sh 30,30\(t5\)'
+.*: Error: illegal operands `cv.sh 15,\(t6\),40'
+.*: Error: illegal operands `cv.sh 45,t3\(t1\)'
+.*: Error: illegal operands `cv.sh 52,\(t2\),t4'
+.*: Error: illegal operands `cv.sw 12,12\(t3\)'
+.*: Error: illegal operands `cv.sw 10,\(t4\),16'
+.*: Error: illegal operands `cv.sw 82,t5\(t5\)'
+.*: Error: illegal operands `cv.sw 14,\(t1\),t6'
+.*: Error: illegal operands `cv.sb t0,10\(12\)'
+.*: Error: illegal operands `cv.sb t1,\(24\),20'
+.*: Error: illegal operands `cv.sb t2,t1\(25\)'
+.*: Error: illegal operands `cv.sb t3,\(75\),t2'
+.*: Error: illegal operands `cv.sh t4,30\(13\)'
+.*: Error: illegal operands `cv.sh t5,\(16\),40'
+.*: Error: illegal operands `cv.sh t6,t3\(31\)'
+.*: Error: illegal operands `cv.sh t0,\(37\),t4'
+.*: Error: illegal operands `cv.sw t1,12\(51\)'
+.*: Error: illegal operands `cv.sw t2,\(43\),16'
+.*: Error: illegal operands `cv.sw t3,t5\(61\)'
+.*: Error: illegal operands `cv.sw t4,\(67\),t6'
+.*: Error: illegal operands `cv.lb t0,12\(12\)'
+.*: Error: illegal operands `cv.lb t1,\(24\),13'
+.*: Error: illegal operands `cv.lb t2,t3\(25\)'
+.*: Error: illegal operands `cv.lb t3,\(75\),t4'
+.*: Error: illegal operands `cv.lbu t4,22\(51\)'
+.*: Error: illegal operands `cv.lbu t5,\(43\),10'
+.*: Error: illegal operands `cv.lbu t6,t5\(61\)'
+.*: Error: illegal operands `cv.lbu t0,\(67\),t6'
+.*: Error: illegal operands `cv.lh t1,19\(13\)'
+.*: Error: illegal operands `cv.lh t2,\(16\),41'
+.*: Error: illegal operands `cv.lh t3,t0\(31\)'
+.*: Error: illegal operands `cv.lh t4,\(37\),t1'
+.*: Error: illegal operands `cv.lhu t5,15\(14\)'
+.*: Error: illegal operands `cv.lhu t6,\(17\),12'
+.*: Error: illegal operands `cv.lhu t0,t2\(14\)'
+.*: Error: illegal operands `cv.lhu t1,\(39\),t3'
+.*: Error: illegal operands `cv.lw t2,4\(24\)'
+.*: Error: illegal operands `cv.lw t3,\(21\),6'
+.*: Error: illegal operands `cv.lw t5,t4\(16\)'
+.*: Error: illegal operands `cv.lw t4,\(47\),t5'
+.*: Error: illegal operands `cv.lb t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lbu t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lh t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lhu t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lw t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.lb t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lbu t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lh t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lhu t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lw t2,-3678\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),-3678'
+.*: Error: illegal operands `cv.lb t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lbu t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lh t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lhu t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lw t2,2048\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),2048'
+.*: Error: illegal operands `cv.lb t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lb t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lbu t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lbu t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lh t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lh t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lhu t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lhu t2,\(t1\),4595'
+.*: Error: illegal operands `cv.lw t2,4595\(t1\)'
+.*: Error: illegal operands `cv.lw t2,\(t1\),4595'
+.*: Error: illegal operands `cv.sb t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sh t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sw t2,-2049\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),-2049'
+.*: Error: illegal operands `cv.sb t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sh t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sw t2,-3669\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),-3669'
+.*: Error: illegal operands `cv.sb t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sh t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sw t2,2048\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),2048'
+.*: Error: illegal operands `cv.sb t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sb t2,\(t1\),5341'
+.*: Error: illegal operands `cv.sh t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sh t2,\(t1\),5341'
+.*: Error: illegal operands `cv.sw t2,5341\(t1\)'
+.*: Error: illegal operands `cv.sw t2,\(t1\),5341'
diff --git a/gas/testsuite/gas/riscv/x-cv-mem-fail.s b/gas/testsuite/gas/riscv/x-cv-mem-fail.s
new file mode 100644
index 00000000000..d35d29f233b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mem-fail.s
@@ -0,0 +1,143 @@
+ # xcvmem - architecture set
+ .option push
+ .option arch, rv32i
+ .include "x-cv-mem.s"
+ .option pop
+
+ # xcvmem - destination operand must be a register
+ cv.lb 20, 10(t1)
+ cv.lb 32, (t2), 15
+ cv.lb 40, t2(t3)
+ cv.lb 28, (t4), t3
+ cv.lbu 16, 20(t5)
+ cv.lbu 20, (t6), 30
+ cv.lbu 44, t4(t1)
+ cv.lbu 48, (t2), t5
+ cv.lh 52, 25(t3)
+ cv.lh 12, (t4), 10
+ cv.lh 16, t6(t5)
+ cv.lh 36, (t6), t1
+ cv.lhu 24, 35(t1)
+ cv.lhu 12, (t2), 13
+ cv.lhu 32, t2(t3)
+ cv.lhu 40, (t4), t3
+ cv.lw 44, 18(t5)
+ cv.lw 48, (t6), 8
+ cv.lw 24, t4(t1)
+ cv.lw 12, (t2), t5
+
+ # xcvmem - source operand must be a register
+ cv.sb 12, 10(t1)
+ cv.sb 14, (t2), 20
+ cv.sb 16, t1(t3)
+ cv.sb 20, (t4), t2
+ cv.sh 30, 30(t5)
+ cv.sh 15, (t6), 40
+ cv.sh 45, t3(t1)
+ cv.sh 52, (t2), t4
+ cv.sw 12, 12(t3)
+ cv.sw 10, (t4), 16
+ cv.sw 82, t5(t5)
+ cv.sw 14, (t1), t6
+
+ # xcvmem - base operand must be a register
+ cv.sb t0, 10(12)
+ cv.sb t1, (24), 20
+ cv.sb t2, t1(25)
+ cv.sb t3, (75), t2
+ cv.sh t4, 30(13)
+ cv.sh t5, (16), 40
+ cv.sh t6, t3(31)
+ cv.sh t0, (37), t4
+ cv.sw t1, 12(51)
+ cv.sw t2, (43), 16
+ cv.sw t3, t5(61)
+ cv.sw t4, (67), t6
+ cv.lb t0, 12(12)
+ cv.lb t1, (24), 13
+ cv.lb t2, t3(25)
+ cv.lb t3, (75), t4
+ cv.lbu t4, 22(51)
+ cv.lbu t5, (43), 10
+ cv.lbu t6, t5(61)
+ cv.lbu t0, (67), t6
+ cv.lh t1, 19(13)
+ cv.lh t2, (16), 41
+ cv.lh t3, t0(31)
+ cv.lh t4, (37), t1
+ cv.lhu t5, 15(14)
+ cv.lhu t6, (17), 12
+ cv.lhu t0, t2(14)
+ cv.lhu t1, (39), t3
+ cv.lw t2, 4(24)
+ cv.lw t3, (21), 6
+ cv.lw t5, t4(16)
+ cv.lw t4, (47), t5
+
+ # xcvmem - offset operand must be in range [-2048, 2047]
+ cv.lb t2, -2049(t1)
+ cv.lb t2, (t1), -2049
+ cv.lbu t2, -2049(t1)
+ cv.lbu t2, (t1), -2049
+ cv.lh t2, -2049(t1)
+ cv.lh t2, (t1), -2049
+ cv.lhu t2, -2049(t1)
+ cv.lhu t2, (t1), -2049
+ cv.lw t2, -2049(t1)
+ cv.lw t2, (t1), -2049
+ cv.lb t2, -3678(t1)
+ cv.lb t2, (t1), -3678
+ cv.lbu t2, -3678(t1)
+ cv.lbu t2, (t1), -3678
+ cv.lh t2, -3678(t1)
+ cv.lh t2, (t1), -3678
+ cv.lhu t2, -3678(t1)
+ cv.lhu t2, (t1), -3678
+ cv.lw t2, -3678(t1)
+ cv.lw t2, (t1), -3678
+ cv.lb t2, 2048(t1)
+ cv.lb t2, (t1), 2048
+ cv.lbu t2, 2048(t1)
+ cv.lbu t2, (t1), 2048
+ cv.lh t2, 2048(t1)
+ cv.lh t2, (t1), 2048
+ cv.lhu t2, 2048(t1)
+ cv.lhu t2, (t1), 2048
+ cv.lw t2, 2048(t1)
+ cv.lw t2, (t1), 2048
+ cv.lb t2, 4595(t1)
+ cv.lb t2, (t1), 4595
+ cv.lbu t2, 4595(t1)
+ cv.lbu t2, (t1), 4595
+ cv.lh t2, 4595(t1)
+ cv.lh t2, (t1), 4595
+ cv.lhu t2, 4595(t1)
+ cv.lhu t2, (t1), 4595
+ cv.lw t2, 4595(t1)
+ cv.lw t2, (t1), 4595
+
+ # xcvmem - offset operand must be in range [-2048, 2047]
+ cv.sb t2, -2049(t1)
+ cv.sb t2, (t1), -2049
+ cv.sh t2, -2049(t1)
+ cv.sh t2, (t1), -2049
+ cv.sw t2, -2049(t1)
+ cv.sw t2, (t1), -2049
+ cv.sb t2, -3669(t1)
+ cv.sb t2, (t1), -3669
+ cv.sh t2, -3669(t1)
+ cv.sh t2, (t1), -3669
+ cv.sw t2, -3669(t1)
+ cv.sw t2, (t1), -3669
+ cv.sb t2, 2048(t1)
+ cv.sb t2, (t1), 2048
+ cv.sh t2, 2048(t1)
+ cv.sh t2, (t1), 2048
+ cv.sw t2, 2048(t1)
+ cv.sw t2, (t1), 2048
+ cv.sb t2, 5341(t1)
+ cv.sb t2, (t1), 5341
+ cv.sh t2, 5341(t1)
+ cv.sh t2, (t1), 5341
+ cv.sw t2, 5341(t1)
+ cv.sw t2, (t1), 5341
diff --git a/gas/testsuite/gas/riscv/x-cv-mem.d b/gas/testsuite/gas/riscv/x-cv-mem.d
new file mode 100644
index 00000000000..7ad9f25242f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mem.d
@@ -0,0 +1,81 @@
+#as: -march=rv32i_xcvmem
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+8003828b[ ]+cv.lb[ ]+t0,\(t2\),-2048
+[ ]+[0-9a-f]+:[ ]+00f30e8b[ ]+cv.lb[ ]+t4,\(t1\),15
+[ ]+[0-9a-f]+:[ ]+7fff0e0b[ ]+cv.lb[ ]+t3,\(t5\),2047
+[ ]+[0-9a-f]+:[ ]+0863b2ab[ ]+cv.lb[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+09c33eab[ ]+cv.lb[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+085f3e2b[ ]+cv.lb[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+0063b2ab[ ]+cv.lb[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+01c33eab[ ]+cv.lb[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+005f3e2b[ ]+cv.lb[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+8003c28b[ ]+cv.lbu[ ]+t0,\(t2\),-2048
+[ ]+[0-9a-f]+:[ ]+00f34e8b[ ]+cv.lbu[ ]+t4,\(t1\),15
+[ ]+[0-9a-f]+:[ ]+7fff4e0b[ ]+cv.lbu[ ]+t3,\(t5\),2047
+[ ]+[0-9a-f]+:[ ]+1863b2ab[ ]+cv.lbu[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+19c33eab[ ]+cv.lbu[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+185f3e2b[ ]+cv.lbu[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+1063b2ab[ ]+cv.lbu[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+11c33eab[ ]+cv.lbu[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+105f3e2b[ ]+cv.lbu[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+8003928b[ ]+cv.lh[ ]+t0,\(t2\),-2048
+[ ]+[0-9a-f]+:[ ]+00f31e8b[ ]+cv.lh[ ]+t4,\(t1\),15
+[ ]+[0-9a-f]+:[ ]+7fff1e0b[ ]+cv.lh[ ]+t3,\(t5\),2047
+[ ]+[0-9a-f]+:[ ]+0a63b2ab[ ]+cv.lh[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+0bc33eab[ ]+cv.lh[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+0a5f3e2b[ ]+cv.lh[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+0263b2ab[ ]+cv.lh[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+03c33eab[ ]+cv.lh[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+025f3e2b[ ]+cv.lh[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+8003d28b[ ]+cv.lhu[ ]+t0,\(t2\),-2048
+[ ]+[0-9a-f]+:[ ]+00f35e8b[ ]+cv.lhu[ ]+t4,\(t1\),15
+[ ]+[0-9a-f]+:[ ]+7fff5e0b[ ]+cv.lhu[ ]+t3,\(t5\),2047
+[ ]+[0-9a-f]+:[ ]+1a63b2ab[ ]+cv.lhu[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+1bc33eab[ ]+cv.lhu[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+1a5f3e2b[ ]+cv.lhu[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+1263b2ab[ ]+cv.lhu[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+13c33eab[ ]+cv.lhu[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+125f3e2b[ ]+cv.lhu[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+8003a28b[ ]+cv.lw[ ]+t0,\(t2\),-2048
+[ ]+[0-9a-f]+:[ ]+00f32e8b[ ]+cv.lw[ ]+t4,\(t1\),15
+[ ]+[0-9a-f]+:[ ]+7fff2e0b[ ]+cv.lw[ ]+t3,\(t5\),2047
+[ ]+[0-9a-f]+:[ ]+0c63b2ab[ ]+cv.lw[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+0dc33eab[ ]+cv.lw[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+0c5f3e2b[ ]+cv.lw[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+0463b2ab[ ]+cv.lw[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+05c33eab[ ]+cv.lw[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+045f3e2b[ ]+cv.lw[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+81f3002b[ ]+cv.sb[ ]+t6,\(t1\),-2048
+[ ]+[0-9a-f]+:[ ]+07d3822b[ ]+cv.sb[ ]+t4,\(t2\),100
+[ ]+[0-9a-f]+:[ ]+7fce8fab[ ]+cv.sb[ ]+t3,\(t4\),2047
+[ ]+[0-9a-f]+:[ ]+2853b32b[ ]+cv.sb[ ]+t0,t1\(t2\)
+[ ]+[0-9a-f]+:[ ]+29d33e2b[ ]+cv.sb[ ]+t4,t3\(t1\)
+[ ]+[0-9a-f]+:[ ]+29cf32ab[ ]+cv.sb[ ]+t3,t0\(t5\)
+[ ]+[0-9a-f]+:[ ]+2053b32b[ ]+cv.sb[ ]+t0,\(t2\),t1
+[ ]+[0-9a-f]+:[ ]+21d33e2b[ ]+cv.sb[ ]+t4,\(t1\),t3
+[ ]+[0-9a-f]+:[ ]+21cf32ab[ ]+cv.sb[ ]+t3,\(t5\),t0
+[ ]+[0-9a-f]+:[ ]+81cf102b[ ]+cv.sh[ ]+t3,\(t5\),-2048
+[ ]+[0-9a-f]+:[ ]+026f9e2b[ ]+cv.sh[ ]+t1,\(t6\),60
+[ ]+[0-9a-f]+:[ ]+7e7e9fab[ ]+cv.sh[ ]+t2,\(t4\),2047
+[ ]+[0-9a-f]+:[ ]+2a6ebe2b[ ]+cv.sh[ ]+t1,t3\(t4\)
+[ ]+[0-9a-f]+:[ ]+2bd333ab[ ]+cv.sh[ ]+t4,t2\(t1\)
+[ ]+[0-9a-f]+:[ ]+2bf3bf2b[ ]+cv.sh[ ]+t6,t5\(t2\)
+[ ]+[0-9a-f]+:[ ]+2263bfab[ ]+cv.sh[ ]+t1,\(t2\),t6
+[ ]+[0-9a-f]+:[ ]+22733f2b[ ]+cv.sh[ ]+t2,\(t1\),t5
+[ ]+[0-9a-f]+:[ ]+23ee3eab[ ]+cv.sh[ ]+t5,\(t3\),t4
+[ ]+[0-9a-f]+:[ ]+806ea02b[ ]+cv.sw[ ]+t1,\(t4\),-2048
+[ ]+[0-9a-f]+:[ ]+07cf222b[ ]+cv.sw[ ]+t3,\(t5\),100
+[ ]+[0-9a-f]+:[ ]+7e63afab[ ]+cv.sw[ ]+t1,\(t2\),2047
+[ ]+[0-9a-f]+:[ ]+2c6eb3ab[ ]+cv.sw[ ]+t1,t2\(t4\)
+[ ]+[0-9a-f]+:[ ]+2dcf33ab[ ]+cv.sw[ ]+t3,t2\(t5\)
+[ ]+[0-9a-f]+:[ ]+2c63bf2b[ ]+cv.sw[ ]+t1,t5\(t2\)
+[ ]+[0-9a-f]+:[ ]+25e3bfab[ ]+cv.sw[ ]+t5,\(t2\),t6
+[ ]+[0-9a-f]+:[ ]+25ceb32b[ ]+cv.sw[ ]+t3,\(t4\),t1
+[ ]+[0-9a-f]+:[ ]+24733eab[ ]+cv.sw[ ]+t2,\(t1\),t4
diff --git a/gas/testsuite/gas/riscv/x-cv-mem.s b/gas/testsuite/gas/riscv/x-cv-mem.s
new file mode 100644
index 00000000000..f232143567f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-mem.s
@@ -0,0 +1,103 @@
+ # xcvmem - lbpost
+ cv.lb t0, (t2), -2048
+ cv.lb t4, (t1), 15
+ cv.lb t3, (t5), 2047
+ # xcvmem - lbrr
+ cv.lb t0, t1(t2)
+ cv.lb t4, t3(t1)
+ cv.lb t3, t0(t5)
+ # xcvmem - lbrrpost
+ cv.lb t0, (t2), t1
+ cv.lb t4, (t1), t3
+ cv.lb t3, (t5), t0
+
+ # xcvmem - lbupost
+ cv.lbu t0, (t2), -2048
+ cv.lbu t4, (t1), 15
+ cv.lbu t3, (t5), 2047
+ # xcvmem - lburr
+ cv.lbu t0, t1(t2)
+ cv.lbu t4, t3(t1)
+ cv.lbu t3, t0(t5)
+ # xcvmem - lburrpost
+ cv.lbu t0, (t2), t1
+ cv.lbu t4, (t1), t3
+ cv.lbu t3, (t5), t0
+
+ # xcvmem - lhpost
+ cv.lh t0, (t2), -2048
+ cv.lh t4, (t1), 15
+ cv.lh t3, (t5), 2047
+ # xcvmem - lhrr
+ cv.lh t0, t1(t2)
+ cv.lh t4, t3(t1)
+ cv.lh t3, t0(t5)
+ # xcvmem - lhrrpost
+ cv.lh t0, (t2), t1
+ cv.lh t4, (t1), t3
+ cv.lh t3, (t5), t0
+
+ # xcvmem - lhupost
+ cv.lhu t0, (t2), -2048
+ cv.lhu t4, (t1), 15
+ cv.lhu t3, (t5), 2047
+ # xcvmem - lhurr
+ cv.lhu t0, t1(t2)
+ cv.lhu t4, t3(t1)
+ cv.lhu t3, t0(t5)
+ # xcvmem - lhurrpost
+ cv.lhu t0, (t2), t1
+ cv.lhu t4, (t1), t3
+ cv.lhu t3, (t5), t0
+
+ # xcvmem - lwpost
+ cv.lw t0, (t2), -2048
+ cv.lw t4, (t1), 15
+ cv.lw t3, (t5), 2047
+ # xcvmem - lwrr
+ cv.lw t0, t1(t2)
+ cv.lw t4, t3(t1)
+ cv.lw t3, t0(t5)
+ # xcvmem - lwrrpost
+ cv.lw t0, (t2), t1
+ cv.lw t4, (t1), t3
+ cv.lw t3, (t5), t0
+
+ # xcvmem - sbpost
+ cv.sb t6, (t1), -2048
+ cv.sb t4, (t2), 100
+ cv.sb t3, (t4), 2047
+ # xcvmem - sbrr
+ cv.sb t0, t1(t2)
+ cv.sb t4, t3(t1)
+ cv.sb t3, t0(t5)
+ # xcvmem - sbrrpost
+ cv.sb t0, (t2), t1
+ cv.sb t4, (t1), t3
+ cv.sb t3, (t5), t0
+
+ # xcvmem - shpost
+ cv.sh t3, (t5), -2048
+ cv.sh t1, (t6), 60
+ cv.sh t2, (t4), 2047
+ # xcvmem - shrr
+ cv.sh t1, t3(t4)
+ cv.sh t4, t2(t1)
+ cv.sh t6, t5(t2)
+ # xcvmem - shrrpost
+ cv.sh t1, (t2), t6
+ cv.sh t2, (t1), t5
+ cv.sh t5, (t3), t4
+
+ # xcvmem - swpost
+ cv.sw t1, (t4), -2048
+ cv.sw t3, (t5), 100
+ cv.sw t1, (t2), 2047
+ # xcvmem - swrr
+ cv.sw t1, t2(t4)
+ cv.sw t3, t2(t5)
+ cv.sw t1, t5(t2)
+ # xcvmem - swrrpost
+ cv.sw t5, (t2), t6
+ cv.sw t3, (t4), t1
+ cv.sw t2, (t1), t4
--
2.39.3 (Apple Git-146)
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