[PATCH 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P
Jiawei
jiawei@iscas.ac.cn
Wed Jul 31 01:50:10 GMT 2024
LGTM,
Founds that we already have a lot of test cases starting with cv, maybe
it would be a good choice to put them in a subdirectory.
BR,
Jiawei
> Spec:https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> Contributors:
> Mary Bennett <mary.@gmail.com <mailto:mary.bennett682@gmail.com>>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> bfd/ChangeLog:
> * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip`
> instruction class.
> (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
> * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`.
> (riscv_ip): Likewise.
> * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension
> for CORE-V.
> * testsuite/gas/riscv/cv-bitmanip-bclr-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclr-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclr-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclr-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclr-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bset-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bset-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bset-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bset-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bset-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-clb-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-clb-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-clb-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-clb-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-clb-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-cnt-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-cnt-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-cnt-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-cnt-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-cnt-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extract-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extract-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extract-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extract-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extract-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractr-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractr-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractr-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractr-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractr-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractu-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractu-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractu-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractu-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractu-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractur-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractur-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractur-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractur-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-extractur-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ff1-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ff1-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ff1-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ff1-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ff1-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-fl1-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-fl1-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-fl1-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-fl1-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-fl1-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insert-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insert-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insert-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insert-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insert-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insertr-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insertr-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insertr-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insertr-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-insertr-pass.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ror-fail.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ror-fail.l: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ror-fail.s: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ror-pass.d: New Test.
> * testsuite/gas/riscv/cv-bitmanip-ror-pass.s: New Test.
>
> include/opcode/ChangeLog:
> * riscv-opc.h: Add corresponding MATCH and MASK macros for
> XCVbitmanip.
> * riscv.h: Add corresponding EXTRACT and ENCODE macros for
> XCVbitmanip.
> (enum riscv_insn_class): Add the XCVbitmanip instruction class.
>
> opcodes/ChangeLog:
> * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`.
> * riscv-opc.c: Add XCVbitmanip instructions.
> ---
> bfd/elfxx-riscv.c | 25 ++++++++------
> gas/config/tc-riscv.c | 26 +++++++++++++++
> gas/doc/c-riscv.texi | 17 ++++++----
> .../gas/riscv/cv-bitmanip-bclr-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-bclr-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-bclr-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-bclr-pass.d | 19 +++++++++++
> .../gas/riscv/cv-bitmanip-bclr-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-bclrr-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-bclrr-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-bclrr-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-bclrr-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-bclrr-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-bitrev-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-bitrev-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-bitrev-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-bitrev-pass.d | 18 ++++++++++
> .../gas/riscv/cv-bitmanip-bitrev-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-bset-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-bset-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-bset-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-bset-pass.d | 19 +++++++++++
> .../gas/riscv/cv-bitmanip-bset-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-bsetr-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-bsetr-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-bsetr-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-bsetr-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-bsetr-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-clb-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-clb-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-clb-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-clb-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-clb-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-cnt-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-cnt-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-cnt-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-cnt-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-cnt-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-extract-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-extract-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-extract-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-extract-pass.d | 19 +++++++++++
> .../gas/riscv/cv-bitmanip-extract-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-extractr-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-extractr-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-extractr-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-extractr-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-extractr-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-extractu-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-extractu-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-extractu-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-extractu-pass.d | 19 +++++++++++
> .../gas/riscv/cv-bitmanip-extractu-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-extractur-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-extractur-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-extractur-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-extractur-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-extractur-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-ff1-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-ff1-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-ff1-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-ff1-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-ff1-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-fl1-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-fl1-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-fl1-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-fl1-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-fl1-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-insert-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-insert-fail.l | 7 ++++
> .../gas/riscv/cv-bitmanip-insert-fail.s | 9 +++++
> .../gas/riscv/cv-bitmanip-insert-pass.d | 19 +++++++++++
> .../gas/riscv/cv-bitmanip-insert-pass.s | 11 +++++++
> .../gas/riscv/cv-bitmanip-insertr-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-insertr-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-insertr-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-insertr-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-insertr-pass.s | 8 +++++
> .../gas/riscv/cv-bitmanip-march-xcvbitmanip.d | 26 +++++++++++++++
> .../gas/riscv/cv-bitmanip-march-xcvbitmanip.s | 17 ++++++++++
> .../gas/riscv/cv-bitmanip-ror-fail.d | 3 ++
> .../gas/riscv/cv-bitmanip-ror-fail.l | 3 ++
> .../gas/riscv/cv-bitmanip-ror-fail.s | 4 +++
> .../gas/riscv/cv-bitmanip-ror-pass.d | 16 +++++++++
> .../gas/riscv/cv-bitmanip-ror-pass.s | 8 +++++
> gas/testsuite/gas/riscv/march-help.l | 5 +--
> include/opcode/riscv-opc.h | 33 +++++++++++++++++++
> include/opcode/riscv.h | 13 ++++++--
> opcodes/riscv-dis.c | 8 +++++
> opcodes/riscv-opc.c | 19 +++++++++++
> 90 files changed, 802 insertions(+), 20 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index b8f314d1c01..1b28b43a51b 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1463,10 +1463,11 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
>
> static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
> {
> - {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> - {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2714,14 +2715,16 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> return riscv_subset_supports (rps, "h");
> - case INSN_CLASS_XCVMAC:
> - return riscv_subset_supports (rps, "xcvmac");
> case INSN_CLASS_XCVALU:
> return riscv_subset_supports (rps, "xcvalu");
> - case INSN_CLASS_XCVELW:
> - return riscv_subset_supports (rps, "xcvelw");
> case INSN_CLASS_XCVBI:
> return riscv_subset_supports (rps, "xcvbi");
> + case INSN_CLASS_XCVBITMANIP:
> + return riscv_subset_supports (rps, "xcvbitmanip");
> + case INSN_CLASS_XCVELW:
> + return riscv_subset_supports (rps, "xcvelw");
> + case INSN_CLASS_XCVMAC:
> + return riscv_subset_supports (rps, "xcvmac");
> case INSN_CLASS_XCVMEM:
> return riscv_subset_supports (rps, "xcvmem");
> case INSN_CLASS_XTHEADBA:
> @@ -2988,14 +2991,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
> return "svinval";
> case INSN_CLASS_H:
> return _("h");
> - case INSN_CLASS_XCVMAC:
> - return "xcvmac";
> case INSN_CLASS_XCVALU:
> return "xcvalu";
> - case INSN_CLASS_XCVELW:
> - return "xcvelw";
> case INSN_CLASS_XCVBI:
> return "xcvbi";
> + case INSN_CLASS_XCVBITMANIP:
> + return "xcvbitmanip";
> + case INSN_CLASS_XCVELW:
> + return "xcvelw";
> + case INSN_CLASS_XCVMAC:
> + return "xcvmac";
> case INSN_CLASS_XCVMEM:
> return "xcvmem";
> case INSN_CLASS_XTHEADBA:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index c09bd429bab..779e0b8d1c7 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1688,6 +1688,12 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case '3':
> used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
> break;
> + case '6':
> + used_bits |= ENCODE_CV_BITMANIP_UIMM5(-1U);
> + break;
> + case '7':
> + used_bits |= ENCODE_CV_BITMANIP_UIMM2(-1U);
> + break;
> default:
> goto unknown_validate_operand;
> }
> @@ -3996,6 +4002,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> ip->insn_opcode
> |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
> continue;
> + case '6':
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + asarg = expr_parse_end;
> + if (imm_expr->X_add_number < 0
> + || imm_expr->X_add_number > 31)
> + break;
> + ip->insn_opcode
> + |= ENCODE_CV_BITMANIP_UIMM5 (imm_expr->X_add_number);
> + continue;
> + case '7':
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + asarg = expr_parse_end;
> + if (imm_expr->X_add_number < 0
> + || imm_expr->X_add_number > 3)
> + break;
> + ip->insn_opcode
> + |= ENCODE_CV_BITMANIP_UIMM2 (imm_expr->X_add_number);
> + continue;
> default:
> goto unknown_riscv_ip_operand;
> }
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index d3966692625..924b70eb7a7 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -740,13 +740,18 @@ extensions supported and provides the location of their
> publicly-released documentation:
>
> @table @r
> -@item XCvMac
> -The XCvMac extension provides instructions for multiply-accumulate operations.
> +@item XCvAlu
> +The XCvAlu extension provides instructions for general ALU operations.
>
> It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
>
> -@item XCvAlu
> -The XCvAlu extension provides instructions for general ALU operations.
> +@item XCvBi
> +The XCvBi extension provides instructions for branch immediate operations.
> +
> +It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
> +
> +@item XcvBitmanip
> +The XcvBitmanip extension provides instructions for bitmanip operations.
>
> It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
>
> @@ -755,8 +760,8 @@ The XCvElw extension provides instructions for event load word operations.
>
> It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
>
> -@item XCvBi
> -The XCvBi extension provides instructions for branch immediate operations.
> +@item XCvMac
> +The XCvMac extension provides instructions for multiply-accumulate operations.
>
> It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
>
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.d
> new file mode 100644
> index 00000000000..cae6d6a6080
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bclr-fail.s
> +#error_output: cv-bitmanip-bclr-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.l
> new file mode 100644
> index 00000000000..d426fee16f6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.bclr x32,x32,20,20'
> +.*: Error: illegal operands `cv.bclr x33,x33,20,20'
> +.*: Error: illegal operands `cv.bclr x6,x7,0,32'
> +.*: Error: illegal operands `cv.bclr x6,x7,32,0'
> +.*: Error: illegal operands `cv.bclr x6,x7,0,-1'
> +.*: Error: illegal operands `cv.bclr x6,x7,-1,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.s
> new file mode 100644
> index 00000000000..32b9dc8d0f8
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.bclr x32, x32, 20, 20
> + cv.bclr x33, x33, 20, 20
> + #Immediate Values Test
> + cv.bclr x6, x7, 0, 32
> + cv.bclr x6, x7, 32, 0
> + cv.bclr x6, x7, 0, -1
> + cv.bclr x6, x7, -1, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.d
> new file mode 100644
> index 00000000000..f42386063e1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bclr-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +
> + 0: 2940105b cv.bclr zero,zero,20,20
> + 4: 294090db cv.bclr ra,ra,20,20
> + 8: 2941115b cv.bclr sp,sp,20,20
> + c: 2944145b cv.bclr s0,s0,20,20
> + 10: 294a1a5b cv.bclr s4,s4,20,20
> + 14: 294f9fdb cv.bclr t6,t6,20,20
> + 18: 0003935b cv.bclr t1,t2,0,0
> + 1c: 3ff3935b cv.bclr t1,t2,31,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.s
> new file mode 100644
> index 00000000000..f93db1a5eea
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.bclr x0, x0, 20, 20
> + cv.bclr x1, x1, 20, 20
> + cv.bclr x2, x2, 20, 20
> + cv.bclr x8, x8, 20, 20
> + cv.bclr x20, x20, 20, 20
> + cv.bclr x31, x31, 20, 20
> + #Immediate Values Test
> + cv.bclr x6, x7, 0, 0
> + cv.bclr x6, x7, 31, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d
> new file mode 100644
> index 00000000000..88eb6bd7f98
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bclrr-fail.s
> +#error_output: cv-bitmanip-bclrr-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l
> new file mode 100644
> index 00000000000..08c7e4b8076
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.bclrr x32,x32,x32'
> +.*: Error: illegal operands `cv.bclrr x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s
> new file mode 100644
> index 00000000000..0a896aeccdf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.bclrr x32, x32, x32
> + cv.bclrr x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d
> new file mode 100644
> index 00000000000..d0f3b30cd25
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bclrr-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 3800302b cv.bclrr zero,zero,zero
> + 4: 3810b0ab cv.bclrr ra,ra,ra
> + 8: 3821312b cv.bclrr sp,sp,sp
> + c: 3884342b cv.bclrr s0,s0,s0
> + 10: 394a3a2b cv.bclrr s4,s4,s4
> + 14: 39ffbfab cv.bclrr t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s
> new file mode 100644
> index 00000000000..31d128797cd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.bclrr x0, x0, x0
> + cv.bclrr x1, x1, x1
> + cv.bclrr x2, x2, x2
> + cv.bclrr x8, x8, x8
> + cv.bclrr x20, x20, x20
> + cv.bclrr x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d
> new file mode 100644
> index 00000000000..75cc17c39b1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bitrev-fail.s
> +#error_output: cv-bitmanip-bitrev-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l
> new file mode 100644
> index 00000000000..77c1c5bb511
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.bitrev x32,x32,2,20'
> +.*: Error: illegal operands `cv.bitrev x33,x33,2,20'
> +.*: Error: illegal operands `cv.bitrev x6,x7,-1,0'
> +.*: Error: illegal operands `cv.bitrev x6,x7,0,-1'
> +.*: Error: illegal operands `cv.bitrev x6,x7,0,32'
> +.*: Error: illegal operands `cv.bitrev x6,x7,4,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s
> new file mode 100644
> index 00000000000..f51a73df492
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.bitrev x32, x32, 2, 20
> + cv.bitrev x33, x33, 2, 20
> + #Immediate Values Test
> + cv.bitrev x6, x7, -1, 0
> + cv.bitrev x6, x7, 0, -1
> + cv.bitrev x6, x7, 0, 32
> + cv.bitrev x6, x7, 4, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d
> new file mode 100644
> index 00000000000..0fa97af4243
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d
> @@ -0,0 +1,18 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bitrev-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: c540105b cv.bitrev zero,zero,2,20
> + 4: c54090db cv.bitrev ra,ra,2,20
> + 8: c541115b cv.bitrev sp,sp,2,20
> + c: c544145b cv.bitrev s0,s0,2,20
> + 10: c54a1a5b cv.bitrev s4,s4,2,20
> + 14: c54f9fdb cv.bitrev t6,t6,2,20
> + 18: c003935b cv.bitrev t1,t2,0,0
> + 1c: c7f3935b cv.bitrev t1,t2,3,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s
> new file mode 100644
> index 00000000000..747516e5007
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.bitrev x0, x0, 2, 20
> + cv.bitrev x1, x1, 2, 20
> + cv.bitrev x2, x2, 2, 20
> + cv.bitrev x8, x8, 2, 20
> + cv.bitrev x20, x20, 2, 20
> + cv.bitrev x31, x31, 2, 20
> + #Immediate Values Test
> + cv.bitrev x6, x7, 0, 0
> + cv.bitrev x6, x7, 3, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.d
> new file mode 100644
> index 00000000000..6ce9dda7d62
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bset-fail.s
> +#error_output: cv-bitmanip-bset-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.l
> new file mode 100644
> index 00000000000..b353f065220
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.bset x32,x32,20,20'
> +.*: Error: illegal operands `cv.bset x33,x33,20,20'
> +.*: Error: illegal operands `cv.bset x6,x7,0,32'
> +.*: Error: illegal operands `cv.bset x6,x7,32,0'
> +.*: Error: illegal operands `cv.bset x6,x7,0,-1'
> +.*: Error: illegal operands `cv.bset x6,x7,-1,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.s
> new file mode 100644
> index 00000000000..e02ed2ee2d9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.bset x32, x32, 20, 20
> + cv.bset x33, x33, 20, 20
> + #Immediate Values Test
> + cv.bset x6, x7, 0, 32
> + cv.bset x6, x7, 32, 0
> + cv.bset x6, x7, 0, -1
> + cv.bset x6, x7, -1, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.d
> new file mode 100644
> index 00000000000..64d05813079
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bset-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +
> + 0: 6940105b cv.bset zero,zero,20,20
> + 4: 694090db cv.bset ra,ra,20,20
> + 8: 6941115b cv.bset sp,sp,20,20
> + c: 6944145b cv.bset s0,s0,20,20
> + 10: 694a1a5b cv.bset s4,s4,20,20
> + 14: 694f9fdb cv.bset t6,t6,20,20
> + 18: 4003935b cv.bset t1,t2,0,0
> + 1c: 7ff3935b cv.bset t1,t2,31,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.s
> new file mode 100644
> index 00000000000..1fc81b7ca3d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.bset x0, x0, 20, 20
> + cv.bset x1, x1, 20, 20
> + cv.bset x2, x2, 20, 20
> + cv.bset x8, x8, 20, 20
> + cv.bset x20, x20, 20, 20
> + cv.bset x31, x31, 20, 20
> + #Immediate Values Test
> + cv.bset x6, x7, 0, 0
> + cv.bset x6, x7, 31, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d
> new file mode 100644
> index 00000000000..15a43c5d596
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bsetr-fail.s
> +#error_output: cv-bitmanip-bsetr-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l
> new file mode 100644
> index 00000000000..e9d8c8c7b3b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.bsetr x32,x32,x32'
> +.*: Error: illegal operands `cv.bsetr x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s
> new file mode 100644
> index 00000000000..8be6ce9f3ed
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.bsetr x32, x32, x32
> + cv.bsetr x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d
> new file mode 100644
> index 00000000000..66a560282ba
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-bsetr-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 3a00302b cv.bsetr zero,zero,zero
> + 4: 3a10b0ab cv.bsetr ra,ra,ra
> + 8: 3a21312b cv.bsetr sp,sp,sp
> + c: 3a84342b cv.bsetr s0,s0,s0
> + 10: 3b4a3a2b cv.bsetr s4,s4,s4
> + 14: 3bffbfab cv.bsetr t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s
> new file mode 100644
> index 00000000000..77f8a9d167a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.bsetr x0, x0, x0
> + cv.bsetr x1, x1, x1
> + cv.bsetr x2, x2, x2
> + cv.bsetr x8, x8, x8
> + cv.bsetr x20, x20, x20
> + cv.bsetr x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.d
> new file mode 100644
> index 00000000000..2597641fba9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-clb-fail.s
> +#error_output: cv-bitmanip-clb-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.l
> new file mode 100644
> index 00000000000..410f26c6b9e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.clb x32,x32'
> +.*: Error: illegal operands `cv.clb x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.s
> new file mode 100644
> index 00000000000..9859cd91f2c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.clb x32, x32
> + cv.clb x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.d
> new file mode 100644
> index 00000000000..6eecfe62021
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-clb-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 4600302b cv.clb zero,zero
> + 4: 4600b0ab cv.clb ra,ra
> + 8: 4601312b cv.clb sp,sp
> + c: 4604342b cv.clb s0,s0
> + 10: 460a3a2b cv.clb s4,s4
> + 14: 460fbfab cv.clb t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.s
> new file mode 100644
> index 00000000000..a3b623e5fbd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.clb x0, x0
> + cv.clb x1, x1
> + cv.clb x2, x2
> + cv.clb x8, x8
> + cv.clb x20, x20
> + cv.clb x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.d
> new file mode 100644
> index 00000000000..8c7a97ea1bc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-cnt-fail.s
> +#error_output: cv-bitmanip-cnt-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.l
> new file mode 100644
> index 00000000000..4f95b5c4638
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.cnt x32,x32'
> +.*: Error: illegal operands `cv.cnt x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.s
> new file mode 100644
> index 00000000000..1dc87fe170e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.cnt x32, x32
> + cv.cnt x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.d
> new file mode 100644
> index 00000000000..0eafe39826f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-cnt-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 4800302b cv.cnt zero,zero
> + 4: 4800b0ab cv.cnt ra,ra
> + 8: 4801312b cv.cnt sp,sp
> + c: 4804342b cv.cnt s0,s0
> + 10: 480a3a2b cv.cnt s4,s4
> + 14: 480fbfab cv.cnt t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.s
> new file mode 100644
> index 00000000000..dd41003b2d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.cnt x0, x0
> + cv.cnt x1, x1
> + cv.cnt x2, x2
> + cv.cnt x8, x8
> + cv.cnt x20, x20
> + cv.cnt x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.d
> new file mode 100644
> index 00000000000..d55bf366601
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extract-fail.s
> +#error_output: cv-bitmanip-extract-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.l
> new file mode 100644
> index 00000000000..eeb8f0695a3
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.extract x32,x32,20,20'
> +.*: Error: illegal operands `cv.extract x33,x33,20,20'
> +.*: Error: illegal operands `cv.extract x6,x7,0,32'
> +.*: Error: illegal operands `cv.extract x6,x7,32,0'
> +.*: Error: illegal operands `cv.extract x6,x7,0,-1'
> +.*: Error: illegal operands `cv.extract x6,x7,-1,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.s
> new file mode 100644
> index 00000000000..aa8989b108d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extract-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.extract x32, x32, 20, 20
> + cv.extract x33, x33, 20, 20
> + #Immediate Values Test
> + cv.extract x6, x7, 0, 32
> + cv.extract x6, x7, 32, 0
> + cv.extract x6, x7, 0, -1
> + cv.extract x6, x7, -1, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.d
> new file mode 100644
> index 00000000000..b5e44a6f0f8
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extract-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +
> + 0: 2940005b cv.extract zero,zero,20,20
> + 4: 294080db cv.extract ra,ra,20,20
> + 8: 2941015b cv.extract sp,sp,20,20
> + c: 2944045b cv.extract s0,s0,20,20
> + 10: 294a0a5b cv.extract s4,s4,20,20
> + 14: 294f8fdb cv.extract t6,t6,20,20
> + 18: 0003835b cv.extract t1,t2,0,0
> + 1c: 3ff3835b cv.extract t1,t2,31,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.s
> new file mode 100644
> index 00000000000..9080800f3f7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extract-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.extract x0, x0, 20, 20
> + cv.extract x1, x1, 20, 20
> + cv.extract x2, x2, 20, 20
> + cv.extract x8, x8, 20, 20
> + cv.extract x20, x20, 20, 20
> + cv.extract x31, x31, 20, 20
> + #Immediate Values Test
> + cv.extract x6, x7, 0, 0
> + cv.extract x6, x7, 31, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.d
> new file mode 100644
> index 00000000000..7d980c818a7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractr-fail.s
> +#error_output: cv-bitmanip-extractr-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.l
> new file mode 100644
> index 00000000000..cdbaa537143
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.extractr x32,x32,x32'
> +.*: Error: illegal operands `cv.extractr x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.s
> new file mode 100644
> index 00000000000..e400c19b37d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.extractr x32, x32, x32
> + cv.extractr x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.d
> new file mode 100644
> index 00000000000..5e2ce8cc7fc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractr-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 3000302b cv.extractr zero,zero,zero
> + 4: 3010b0ab cv.extractr ra,ra,ra
> + 8: 3021312b cv.extractr sp,sp,sp
> + c: 3084342b cv.extractr s0,s0,s0
> + 10: 314a3a2b cv.extractr s4,s4,s4
> + 14: 31ffbfab cv.extractr t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.s
> new file mode 100644
> index 00000000000..5c937dc9439
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractr-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.extractr x0, x0, x0
> + cv.extractr x1, x1, x1
> + cv.extractr x2, x2, x2
> + cv.extractr x8, x8, x8
> + cv.extractr x20, x20, x20
> + cv.extractr x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.d
> new file mode 100644
> index 00000000000..26315df0782
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractu-fail.s
> +#error_output: cv-bitmanip-extractu-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.l
> new file mode 100644
> index 00000000000..4ef54335e16
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.extractu x32,x32,20,20'
> +.*: Error: illegal operands `cv.extractu x33,x33,20,20'
> +.*: Error: illegal operands `cv.extractu x6,x7,0,32'
> +.*: Error: illegal operands `cv.extractu x6,x7,32,0'
> +.*: Error: illegal operands `cv.extractu x6,x7,0,-1'
> +.*: Error: illegal operands `cv.extractu x6,x7,-1,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.s
> new file mode 100644
> index 00000000000..ac77c9c2fe7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.extractu x32, x32, 20, 20
> + cv.extractu x33, x33, 20, 20
> + #Immediate Values Test
> + cv.extractu x6, x7, 0, 32
> + cv.extractu x6, x7, 32, 0
> + cv.extractu x6, x7, 0, -1
> + cv.extractu x6, x7, -1, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.d
> new file mode 100644
> index 00000000000..40981c3ba73
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractu-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +
> + 0: 6940005b cv.extractu zero,zero,20,20
> + 4: 694080db cv.extractu ra,ra,20,20
> + 8: 6941015b cv.extractu sp,sp,20,20
> + c: 6944045b cv.extractu s0,s0,20,20
> + 10: 694a0a5b cv.extractu s4,s4,20,20
> + 14: 694f8fdb cv.extractu t6,t6,20,20
> + 18: 4003835b cv.extractu t1,t2,0,0
> + 1c: 7ff3835b cv.extractu t1,t2,31,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.s
> new file mode 100644
> index 00000000000..1df3c3c0eb5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractu-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.extractu x0, x0, 20, 20
> + cv.extractu x1, x1, 20, 20
> + cv.extractu x2, x2, 20, 20
> + cv.extractu x8, x8, 20, 20
> + cv.extractu x20, x20, 20, 20
> + cv.extractu x31, x31, 20, 20
> + #Immediate Values Test
> + cv.extractu x6, x7, 0, 0
> + cv.extractu x6, x7, 31, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.d
> new file mode 100644
> index 00000000000..548f3b908f9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractur-fail.s
> +#error_output: cv-bitmanip-extractur-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.l
> new file mode 100644
> index 00000000000..c2ed50f80d3
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.extractur x32,x32,x32'
> +.*: Error: illegal operands `cv.extractur x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.s
> new file mode 100644
> index 00000000000..bffdd0f1e6e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.extractur x32, x32, x32
> + cv.extractur x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.d
> new file mode 100644
> index 00000000000..2898d82e055
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-extractur-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 3200302b cv.extractur zero,zero,zero
> + 4: 3210b0ab cv.extractur ra,ra,ra
> + 8: 3221312b cv.extractur sp,sp,sp
> + c: 3284342b cv.extractur s0,s0,s0
> + 10: 334a3a2b cv.extractur s4,s4,s4
> + 14: 33ffbfab cv.extractur t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.s
> new file mode 100644
> index 00000000000..de4f3114358
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-extractur-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.extractur x0, x0, x0
> + cv.extractur x1, x1, x1
> + cv.extractur x2, x2, x2
> + cv.extractur x8, x8, x8
> + cv.extractur x20, x20, x20
> + cv.extractur x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.d
> new file mode 100644
> index 00000000000..00b421cee97
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-ff1-fail.s
> +#error_output: cv-bitmanip-ff1-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.l
> new file mode 100644
> index 00000000000..3ab016dd3ac
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.ff1 x32,x32'
> +.*: Error: illegal operands `cv.ff1 x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.s
> new file mode 100644
> index 00000000000..f28ebe6b5e3
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.ff1 x32, x32
> + cv.ff1 x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.d
> new file mode 100644
> index 00000000000..37f5d7cc405
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-ff1-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 4200302b cv.ff1 zero,zero
> + 4: 4200b0ab cv.ff1 ra,ra
> + 8: 4201312b cv.ff1 sp,sp
> + c: 4204342b cv.ff1 s0,s0
> + 10: 420a3a2b cv.ff1 s4,s4
> + 14: 420fbfab cv.ff1 t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.s
> new file mode 100644
> index 00000000000..d4b09cb9178
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ff1-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.ff1 x0, x0
> + cv.ff1 x1, x1
> + cv.ff1 x2, x2
> + cv.ff1 x8, x8
> + cv.ff1 x20, x20
> + cv.ff1 x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.d
> new file mode 100644
> index 00000000000..fc9554af038
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-fl1-fail.s
> +#error_output: cv-bitmanip-fl1-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.l
> new file mode 100644
> index 00000000000..ca78231d3e9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.fl1 x32,x32'
> +.*: Error: illegal operands `cv.fl1 x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.s
> new file mode 100644
> index 00000000000..1fafd9c0833
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.fl1 x32, x32
> + cv.fl1 x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.d
> new file mode 100644
> index 00000000000..52f90d8ba25
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-fl1-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 4400302b cv.fl1 zero,zero
> + 4: 4400b0ab cv.fl1 ra,ra
> + 8: 4401312b cv.fl1 sp,sp
> + c: 4404342b cv.fl1 s0,s0
> + 10: 440a3a2b cv.fl1 s4,s4
> + 14: 440fbfab cv.fl1 t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.s
> new file mode 100644
> index 00000000000..5fcdf80cb6a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-fl1-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.fl1 x0, x0
> + cv.fl1 x1, x1
> + cv.fl1 x2, x2
> + cv.fl1 x8, x8
> + cv.fl1 x20, x20
> + cv.fl1 x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.d
> new file mode 100644
> index 00000000000..c6928b74270
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-insert-fail.s
> +#error_output: cv-bitmanip-insert-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.l
> new file mode 100644
> index 00000000000..51adfcd99cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.insert x32,x32,20,20'
> +.*: Error: illegal operands `cv.insert x33,x33,20,20'
> +.*: Error: illegal operands `cv.insert x6,x7,0,32'
> +.*: Error: illegal operands `cv.insert x6,x7,32,0'
> +.*: Error: illegal operands `cv.insert x6,x7,0,-1'
> +.*: Error: illegal operands `cv.insert x6,x7,-1,0'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.s
> new file mode 100644
> index 00000000000..e907461defe
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insert-fail.s
> @@ -0,0 +1,9 @@
> +target:
> + #Register Tests
> + cv.insert x32, x32, 20, 20
> + cv.insert x33, x33, 20, 20
> + #Immediate Values Test
> + cv.insert x6, x7, 0, 32
> + cv.insert x6, x7, 32, 0
> + cv.insert x6, x7, 0, -1
> + cv.insert x6, x7, -1, 0
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.d
> new file mode 100644
> index 00000000000..b46744b37cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-insert-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +
> + 0: a940005b cv.insert zero,zero,20,20
> + 4: a94080db cv.insert ra,ra,20,20
> + 8: a941015b cv.insert sp,sp,20,20
> + c: a944045b cv.insert s0,s0,20,20
> + 10: a94a0a5b cv.insert s4,s4,20,20
> + 14: a94f8fdb cv.insert t6,t6,20,20
> + 18: 8003835b cv.insert t1,t2,0,0
> + 1c: bff3835b cv.insert t1,t2,31,31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.s
> new file mode 100644
> index 00000000000..0de34d64419
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insert-pass.s
> @@ -0,0 +1,11 @@
> +target:
> + #Register Tests
> + cv.insert x0, x0, 20, 20
> + cv.insert x1, x1, 20, 20
> + cv.insert x2, x2, 20, 20
> + cv.insert x8, x8, 20, 20
> + cv.insert x20, x20, 20, 20
> + cv.insert x31, x31, 20, 20
> + #Immediate Values Test
> + cv.insert x6, x7, 0, 0
> + cv.insert x6, x7, 31, 31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.d
> new file mode 100644
> index 00000000000..285c503db26
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-insertr-fail.s
> +#error_output: cv-bitmanip-insertr-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.l
> new file mode 100644
> index 00000000000..59f606f60f6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.insertr x32,x32,x32'
> +.*: Error: illegal operands `cv.insertr x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.s
> new file mode 100644
> index 00000000000..f6e333f9f1a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.insertr x32, x32, x32
> + cv.insertr x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.d
> new file mode 100644
> index 00000000000..214f63a8834
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-insertr-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 3400302b cv.insertr zero,zero,zero
> + 4: 3410b0ab cv.insertr ra,ra,ra
> + 8: 3421312b cv.insertr sp,sp,sp
> + c: 3484342b cv.insertr s0,s0,s0
> + 10: 354a3a2b cv.insertr s4,s4,s4
> + 14: 35ffbfab cv.insertr t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.s
> new file mode 100644
> index 00000000000..64f54059f76
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-insertr-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.insertr x0, x0, x0
> + cv.insertr x1, x1, x1
> + cv.insertr x2, x2, x2
> + cv.insertr x8, x8, x8
> + cv.insertr x20, x20, x20
> + cv.insertr x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.d b/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.d
> new file mode 100644
> index 00000000000..aa3ac911330
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.d
> @@ -0,0 +1,26 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-march-xcvbitmanip.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+0:[ ]+2943835b[ ]+cv.extract t1,t2,20,20
> +[ ]+4:[ ]+6943835b[ ]+cv.extractu t1,t2,20,20
> +[ ]+8:[ ]+a943835b[ ]+cv.insert t1,t2,20,20
> +[ ]+c:[ ]+2943935b[ ]+cv.bclr t1,t2,20,20
> +[ ]+10:[ ]+6943935b[ ]+cv.bset t1,t2,20,20
> +[ ]+14:[ ]+c743935b[ ]+cv.bitrev t1,t2,3,20
> +[ ]+18:[ ]+307332ab[ ]+cv.extractr t0,t1,t2
> +[ ]+1c:[ ]+327332ab[ ]+cv.extractur t0,t1,t2
> +[ ]+20:[ ]+347332ab[ ]+cv.insertr t0,t1,t2
> +[ ]+24:[ ]+387332ab[ ]+cv.bclrr t0,t1,t2
> +[ ]+28:[ ]+3a7332ab[ ]+cv.bsetr t0,t1,t2
> +[ ]+2c:[ ]+407332ab[ ]+cv.ror t0,t1,t2
> +[ ]+30:[ ]+4203b32b[ ]+cv.ff1 t1,t2
> +[ ]+34:[ ]+4403b32b[ ]+cv.fl1 t1,t2
> +[ ]+38:[ ]+4603b32b[ ]+cv.clb t1,t2
> +[ ]+3c:[ ]+4803b32b[ ]+cv.cnt t1,t2
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.s b/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.s
> new file mode 100644
> index 00000000000..5116f0b82be
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-march-xcvbitmanip.s
> @@ -0,0 +1,17 @@
> +target:
> + cv.extract x6, x7, 20, 20
> + cv.extractu x6, x7, 20, 20
> + cv.insert x6, x7, 20, 20
> + cv.bclr x6, x7, 20, 20
> + cv.bset x6, x7, 20, 20
> + cv.bitrev x6, x7, 3, 20
> + cv.extractr x5, x6, x7
> + cv.extractur x5, x6, x7
> + cv.insertr x5, x6, x7
> + cv.bclrr x5, x6, x7
> + cv.bsetr x5, x6, x7
> + cv.ror x5, x6, x7
> + cv.ff1 x6, x7
> + cv.fl1 x6, x7
> + cv.clb x6, x7
> + cv.cnt x6, x7
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.d b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.d
> new file mode 100644
> index 00000000000..a3ed0866444
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-ror-fail.s
> +#error_output: cv-bitmanip-ror-fail.l
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.l b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.l
> new file mode 100644
> index 00000000000..7f2da523276
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.ror x32,x32,x32'
> +.*: Error: illegal operands `cv.ror x33,x33,x33'
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.s b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.s
> new file mode 100644
> index 00000000000..0e7cb9b3c3e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ror-fail.s
> @@ -0,0 +1,4 @@
> +target:
> + #Boundary Register Tests
> + cv.ror x32, x32, x32
> + cv.ror x33, x33, x33
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.d b/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.d
> new file mode 100644
> index 00000000000..3d2e6769820
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.d
> @@ -0,0 +1,16 @@
> +#as: -march=rv32i_xcvbitmanip
> +#source: cv-bitmanip-ror-pass.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> + 0: 4000302b cv.ror zero,zero,zero
> + 4: 4010b0ab cv.ror ra,ra,ra
> + 8: 4021312b cv.ror sp,sp,sp
> + c: 4084342b cv.ror s0,s0,s0
> + 10: 414a3a2b cv.ror s4,s4,s4
> + 14: 41ffbfab cv.ror t6,t6,t6
> diff --git a/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.s b/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.s
> new file mode 100644
> index 00000000000..d933153be99
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-bitmanip-ror-pass.s
> @@ -0,0 +1,8 @@
> +target:
> + #Register Tests
> + cv.ror x0, x0, x0
> + cv.ror x1, x1, x1
> + cv.ror x2, x2, x2
> + cv.ror x8, x8, x8
> + cv.ror x20, x20, x20
> + cv.ror x31, x31, x31
> diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
> index 97521c7c02b..8ade9093d13 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -129,10 +129,11 @@ All available -march extensions for RISC-V:
> svinval 1.0
> svnapot 1.0
> svpbmt 1.0
> - xcvmac 1.0
> xcvalu 1.0
> - xcvelw 1.0
> xcvbi 1.0
> + xcvbitmanip 1.0
> + xcvelw 1.0
> + xcvmac 1.0
> xcvmem 1.0
> xtheadba 1.0
> xtheadbb 1.0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index f0e1d99a5a9..e039cf5482a 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2552,6 +2552,39 @@
> #define MATCH_CV_SHRR 0x2a00302b
> #define MASK_CV_SWRR 0xfe00707f
> #define MATCH_CV_SWRR 0x2c00302b
> +/* Vendor-specific (CORE-V) Xcvbitmanip instructions. */
> +#define MATCH_CV_EXTRACTR 0x3000302b
> +#define MATCH_CV_EXTRACTUR 0x3200302b
> +#define MATCH_CV_INSERTR 0x3400302b
> +#define MATCH_CV_BCLRR 0x3800302b
> +#define MATCH_CV_BSETR 0x3a00302b
> +#define MATCH_CV_ROR 0x4000302b
> +#define MATCH_CV_FF1 0x4200302b
> +#define MATCH_CV_FL1 0x4400302b
> +#define MATCH_CV_CLB 0x4600302b
> +#define MATCH_CV_CNT 0x4800302b
> +#define MATCH_CV_EXTRACT 0x5b
> +#define MATCH_CV_EXTRACTU 0x4000005b
> +#define MATCH_CV_INSERT 0x8000005b
> +#define MATCH_CV_BCLR 0x105b
> +#define MATCH_CV_BSET 0x4000105b
> +#define MATCH_CV_BITREV 0xc000105b
> +#define MASK_CV_EXTRACTR 0xfe00707f
> +#define MASK_CV_EXTRACTUR 0xfe00707f
> +#define MASK_CV_INSERTR 0xfe00707f
> +#define MASK_CV_BCLRR 0xfe00707f
> +#define MASK_CV_BSETR 0xfe00707f
> +#define MASK_CV_ROR 0xfe00707f
> +#define MASK_CV_FF1 0xfff0707f
> +#define MASK_CV_FL1 0xfff0707f
> +#define MASK_CV_CLB 0xfff0707f
> +#define MASK_CV_CNT 0xfff0707f
> +#define MASK_CV_EXTRACT 0xc000707f
> +#define MASK_CV_EXTRACTU 0xc000707f
> +#define MASK_CV_INSERT 0xc000707f
> +#define MASK_CV_BCLR 0xc000707f
> +#define MASK_CV_BSET 0xc000707f
> +#define MASK_CV_BITREV 0xf800707f
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> #define MATCH_TH_ADDSL 0x0000100b
> #define MASK_TH_ADDSL 0xf800707f
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index fedd47837e4..54380049961 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -122,6 +122,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
> (RV_X(x, 25, 5))
> #define EXTRACT_CV_BI_IMM5(x) \
> (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
> +#define EXTRACT_CV_BITMANIP_UIMM5(x) \
> + (RV_X(x, 25, 5))
> +#define EXTRACT_CV_BITMANIP_UIMM2(x) \
> + (RV_X(x, 25, 2))
>
> #define ENCODE_ITYPE_IMM(x) \
> (RV_X(x, 0, 12) << 20)
> @@ -180,6 +184,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
> (RV_X(x, 0, 5) << 20)
> #define ENCODE_CV_IS3_UIMM5(x) \
> (RV_X(x, 0, 5) << 25)
> +#define ENCODE_CV_BITMANIP_UIMM5(x) \
> + (RV_X(x, 0, 5) << 25)
> +#define ENCODE_CV_BITMANIP_UIMM2(x) \
> + (RV_X(x, 0, 2) << 25)
>
> #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
> #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
> @@ -495,10 +503,11 @@ enum riscv_insn_class
> INSN_CLASS_ZACAS,
> INSN_CLASS_ZABHA_AND_ZACAS,
> INSN_CLASS_H,
> - INSN_CLASS_XCVMAC,
> INSN_CLASS_XCVALU,
> - INSN_CLASS_XCVELW,
> INSN_CLASS_XCVBI,
> + INSN_CLASS_XCVBITMANIP,
> + INSN_CLASS_XCVELW,
> + INSN_CLASS_XCVMAC,
> INSN_CLASS_XCVMEM,
> INSN_CLASS_XTHEADBA,
> INSN_CLASS_XTHEADBB,
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 9c5e6ce1e69..f292fc77741 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -803,6 +803,14 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> print (info->stream, dis_style_immediate, "%d",
> ((int) EXTRACT_CV_BI_IMM5 (l)));
> break;
> + case '6':
> + print (info->stream, dis_style_immediate, "%d",
> + ((int) EXTRACT_CV_BITMANIP_UIMM5 (l)));
> + break;
> + case '7':
> + print (info->stream, dis_style_immediate, "%d",
> + ((int) EXTRACT_CV_BITMANIP_UIMM2 (l)));
> + break;
> default:
> goto undefined_modifier;
> }
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 14ec2903cdd..d1cd57556b5 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2287,6 +2287,25 @@ const struct riscv_opcode riscv_opcodes[] =
> {"cv.sw", 0, INSN_CLASS_XCVMEM, "t,d(s)", MATCH_CV_SWRR, MASK_CV_SWRR, match_opcode, 0},
> {"cv.sw", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SWRRPOST, MASK_CV_SWRRPOST, match_opcode, 0},
>
> +/* Vendor-specific (CORE-V) Xcvbitmanip instructions. */
> +{"cv.extractr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_EXTRACTR, MASK_CV_EXTRACTR, match_opcode, 0},
> +{"cv.extractur", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_EXTRACTUR, MASK_CV_EXTRACTUR, match_opcode, 0},
> +{"cv.insertr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_INSERTR, MASK_CV_INSERTR, match_opcode, 0},
> +{"cv.bclrr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_BCLRR, MASK_CV_BCLRR, match_opcode, 0},
> +{"cv.bsetr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_BSETR, MASK_CV_BSETR, match_opcode, 0},
> +{"cv.ror", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_ROR, MASK_CV_ROR, match_opcode, 0},
> +{"cv.ff1", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_FF1, MASK_CV_FF1, match_opcode, 0},
> +{"cv.fl1", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_FL1, MASK_CV_FL1, match_opcode, 0},
> +{"cv.clb", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_CLB, MASK_CV_CLB, match_opcode, 0},
> +{"cv.cnt", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_CNT, MASK_CV_CNT, match_opcode, 0},
> +
> +{"cv.extract", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_EXTRACT, MASK_CV_EXTRACT, match_opcode, 0},
> +{"cv.extractu", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_EXTRACTU, MASK_CV_EXTRACTU, match_opcode, 0},
> +{"cv.insert", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_INSERT, MASK_CV_INSERT, match_opcode, 0},
> +{"cv.bclr", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_BCLR, MASK_CV_BCLR, match_opcode, 0},
> +{"cv.bset", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_BSET, MASK_CV_BSET, match_opcode, 0},
> +{"cv.bitrev", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc7,Xc2", MATCH_CV_BITREV, MASK_CV_BITREV, match_opcode, 0},
> +
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
>
> --
> 2.43.0
>
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