[PATCH] opcodes/x86: fix minor missed styling case

[Cui, Lili]

> On 24.07.2024 04:31, Cui, Lili wrote:
> >>> I noticed that the x86 instruction:
> >>>
> >>>   sar    $0x1,%rsi
> >>>
> >>> would fail to style the '$0x1' as an immediate.  This commit fixes that case.
> >>>
> >
> > I'm afraid it is not a bug, it is to distinguish between the two formats below.
> >
> > sar    r/m8, 1
> > sar    r/m8, imm8
> 
> It is a bug, but it also is a bug to change 1 to 0x1, as that way said distinction
> goes away. (I also don't immediately see how the code change alone would
> pass the testsuite; I'm pretty sure we have expectations which would have
> required adjustment, which would have made more obvious that the change
> wants doing differently.)
> 
Jan, do you have any suggestions on how to distinguish between IMM1 and IMM8? It seems that the current distinction can easily cause confusion.

Currently,
Intel format: disassembler prints 1 for Imm1 and 0x1 for Imm8.
ATT  format: disassembler prints $1 for Imm1 and $0x1 for Imm8.


Thanks,
Lili.