[PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions.

[Srinath Parvathaneni]

Hi,

On 7/15/24 07:14, Jan Beulich wrote:
> On 08.07.2024 17:36, Srinath Parvathaneni wrote:
>>
>> This patch adds support for following sme2.1 movaz instructions and
>> the spec is available here [1].
>>
>> 1. MOVAZ (array to vector, two registers).
>> 2. MOVAZ (array to vector, four registers).
>> 3. MOVAZ (tile to vector, single).
>>
>> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
>> ---
>>   gas/config/tc-aarch64.c                  |  1 +
>>   gas/testsuite/gas/aarch64/sme2p1-3-bad.d |  4 ++
>>   gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 ++++++++++
>>   gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +++++++
>>   gas/testsuite/gas/aarch64/sme2p1-3.d     | 26 ++++++++
>>   gas/testsuite/gas/aarch64/sme2p1-3.s     | 19 ++++++
>>   gas/testsuite/gas/aarch64/sme2p1-4-bad.d |  4 ++
>>   gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 ++++++++++++++++++++++++
>>   gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 +++++++++++++++
>>   gas/testsuite/gas/aarch64/sme2p1-4.d     | 53 +++++++++++++++++
>>   gas/testsuite/gas/aarch64/sme2p1-4.s     | 48 +++++++++++++++
>>   include/opcode/aarch64.h                 |  1 +
>>   opcodes/aarch64-asm.c                    | 43 ++++++++++++++
>>   opcodes/aarch64-asm.h                    |  1 +
>>   opcodes/aarch64-dis.c                    | 49 +++++++++++++++
>>   opcodes/aarch64-dis.h                    |  1 +
>>   opcodes/aarch64-opc.c                    | 13 +++-
>>   opcodes/aarch64-opc.h                    |  4 ++
>>   opcodes/aarch64-tbl.h                    | 19 ++++++
>>   19 files changed, 459 insertions(+), 1 deletion(-)
>>   create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
>>   create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
>>   create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
>>   create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
> 
> In here expectations are for the optional ", VGx..." to be present. Elsewhere
> in disassembly I think optional parts are omitted, at least by default. Except
> that I notice that this same construct looks to uniformly be there when SME2
> (or newer) insns have it. Perhaps I'm unaware of an earlier discussion on this
> ...
> 
> Jan
The spec states "The vector group symbol is preferred for disassembly, 
but optional in assembler source code.", so we have added the 
disassembly with "VGx...".

But with other optional argument cases, as you mentioned if optional 
argument is present (and set to default) or ignored in the assembly, we 
have dropped the optional argument from the disassembly.

Regards,
Srinath