[PATCH 0/2] s390: Simplify (dis)assembly of operands with const bits

[Jens Remus]

Simplify the s390 assembler and disassembler logic for processing of
instruction operands with constant bits.

Patch 1 removes the need for the operand flags OR1, OR2, and OR8 to OR
the respective constant value into the operand during assembly and mask
it during disassembly. The constant bits are already contained in the
insn template and can be used from there for both purposes.

Patch 2 relaxes the operand constraints of the extended mnemonics
risbg[n]z, risb{h|l}gz, and {rns|ros|rxs}bgt. Out of the I3, I4, and I5
operands only the I3/I4 operand containing the Z/T-bit was restricted
to the exact 6/5-bit width. All other instructions only adhere to the
instruction format operand constraints. This aligns GNU Assembler to
the LLVM Assembler on s390x and removes the operands U5 and U6.

Regards,
Jens

Jens Remus (2):
  s390: Simplify (dis)assembly of insn operands with const bits
  s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand
    constraints

 gas/config/tc-s390.c               |  7 -----
 gas/testsuite/gas/s390/zarch-z10.d | 12 +++----
 gas/testsuite/gas/s390/zarch-z10.s | 12 +++----
 include/opcode/s390.h              |  4 ---
 opcodes/s390-dis.c                 | 14 +++++----
 opcodes/s390-opc.c                 | 50 +++++++++++-------------------
 6 files changed, 38 insertions(+), 61 deletions(-)

-- 
2.40.1