[PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction.

[Richard Earnshaw (lists)]

On 04/07/2024 13:40, Srinath Parvathaneni wrote:
> 
> This patch adds support for followign SVE2p1 instruction, spec is available here [1].
> 
> 1. PMOV (to vector)
> 2. PMOV (to predicate)
> 
> Both pmov (to vector) and pmov (to predicate) have destination scalable vector
> register and source scalable vector register respectively as an operand with no
> suffix and optional index. To handle this case we have added 8 new operands in
> this patch.
> 
> AARCH64_OPND_SVE_Zn0_INDEX,      /* Zn[index], bits [9:5].  */
> AARCH64_OPND_SVE_Zn1_17_INDEX,    /* Zn[index], bits [9:5,17].  */
> AARCH64_OPND_SVE_Zn2_18_INDEX,    /* Zn[index], bits [9:5,18:17].  */
> AARCH64_OPND_SVE_Zn3_22_INDEX,    /* Zn[index], bits [9:5,18:17,22].  */
> AARCH64_OPND_SVE_Zd0_INDEX,      /* Zn[index], bits [4:0].  */
> AARCH64_OPND_SVE_Zd1_17_INDEX,    /* Zn[index], bits [4:0,17].  */
> AARCH64_OPND_SVE_Zd2_18_INDEX,    /* Zn[index], bits [4:0,18:17].  */
> AARCH64_OPND_SVE_Zd3_22_INDEX,    /* Zn[index], bits [4:0,18:17,22].  */
> 
> Since the index of the <Zd> operand is optional, the index part is
> dropped in disassembly in both the cases of "no index" or "zero index".
> 
> As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
>              PMOV <Pn>.D, <Zd>{[<imm>]}
> 
> Example1:
> 	Assembly: pmov z5[0], p6.d
> 	Disassembly: pmov z5, p6.d
> 
>         Assembly: pmov z5, p6.d
>         Disassembly: pmov z5, p6.d
> 
> Example2:
> 	Assembly: pmov p4.b, z5[0]
> 	Disassembly: pmov p4.b, z5
> 
>         Assembly: pmov p4.b, z5
>         Disassembly: pmov p4.b, z5
> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
> ---
>  gas/config/tc-aarch64.c                      |  28 ++++-
>  gas/testsuite/gas/aarch64/sve2p1-7-invalid.d |   3 +
>  gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 +++++++++++++++++++
>  gas/testsuite/gas/aarch64/sve2p1-7-invalid.s |  76 ++++++++++++
>  gas/testsuite/gas/aarch64/sve2p1-7.d         |  64 ++++++++++
>  gas/testsuite/gas/aarch64/sve2p1-7.s         |  63 ++++++++++
>  include/opcode/aarch64.h                     |   8 ++
>  opcodes/aarch64-opc.c                        |  34 +++++-
>  opcodes/aarch64-opc.h                        |   2 +
>  opcodes/aarch64-tbl.h                        |  54 ++++++++-
>  10 files changed, 440 insertions(+), 10 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
>  create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
>  create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
>  create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.d
>  create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.s
> 

+   FLAGS includes PTR_OPTIONAL_INDEX, which has been introduced to parse
+   instructions with optional index operands.  */

This will read strangely ten years from now.  Just say:

   FLAGS includes PTR_OPTIONAL_INDEX to handle instructions with optional index operands.

R.