[PATCH] x86: Add {load}/{store} tests for apx instructions.
Cui, Lili
lili.cui@intel.com
Tue Jul 2 07:09:21 GMT 2024
> On 01.07.2024 15:42, Cui, Lili wrote:
> >> Having reached the end of the file: What about CTESTcc and CCMPcc?
> >>
> >
When adding swap test cases for CTESTcc, I found that it does not support swapping operands, but test, {evex} test and ctest template insns all have D, which does not match the SDM/APX spec, I want to remove D for them. I'm a bit unsure if there's any particular reason why the legacy test added D ?
test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > I met some issues when adding CTESTcc and CCMPcc.
> >
> > For example, the disassembler for "{load} ccmpbl %edx, %eax" now looks a bit
> weird.
> >
> > "ccmpbl {dfv=}.s %edx,%eax"
>
> Well ... Something clearly needs doing about this. I'm now even more convinced
> we want tests for these.
>
Indeed, I added a macro %SW to indicate operands were swapped when suffix_always is true. Are you ok with it?
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -940,8 +940,8 @@ static const struct dis386 evex_table[][256] = {
/* 38 */
{ "%NEccmp%SCB%DF", { Eb, Gb }, 0 },
{ "%NEccmp%SCS%DF", { Ev, Gv }, PREFIX_NP_OR_DATA },
- { "%NEccmp%SCB%DF", { Gb, EbS }, 0 },
- { "%NEccmp%SCS%DF", { Gv, EvS }, PREFIX_NP_OR_DATA },
+ { "%NEccmp%SCB%SW%DF", { Gb, Eb }, 0 },
+ { "%NEccmp%SCS%SW%DF", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 978440fa3f1..483cc16ff16 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1809,6 +1809,8 @@ struct dis386 {
in MAP4.
"ZU" => print 'zu' if EVEX.ZU=1.
"SC" => print suffix SCC for SCC insns
+ "SW" => print '.s' to indicate operands were swapped when suffix_always is
+ true.
"YK" keep unused, to avoid ambiguity with the combined use of Y and K.
"YX" keep unused, to avoid ambiguity with the combined use of Y and X.
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
@@ -10927,6 +10929,14 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
*ins->obufp++ = ins->vex.w ? 'd': 's';
else if (last[0] == 'B')
*ins->obufp++ = ins->vex.w ? 'w': 'b';
+ else if (last[0] == 'S')
+ {
+ if (sizeflag & SUFFIX_ALWAYS)
+ {
+ *ins->obufp++ = '.';
+ *ins->obufp++ = 's';
+ }
+ }
Thanks,
Lili.
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