[PATCH V2] Support APX CFCMOV

[Jan Beulich]

On 01.07.2024 09:32, Cui, Lili wrote:
>> On 01.07.2024 08:37, Cui, Lili wrote:
>>>> On 25.06.2024 11:56, Cui, Lili wrote:
>>>>> @@ -14039,3 +14047,26 @@ JMPABS_Fixup (instr_info *ins, int
>>>>> bytemode,
>>>> int sizeflag)
>>>>>      return OP_IMREG (ins, bytemode, sizeflag);
>>>>>    return OP_OFF64 (ins, bytemode, sizeflag);  }
>>>>> +
>>>>> +static bool
>>>>> +CFCMOV_Fixup_op (instr_info *ins, int opnd, int sizeflag) {
>>>>> +  /* EVEX.NF is used as a direction bit in the 2-operand case to reverse
>> the
>>>>> +     source and destination operands.  */
>>>>> +  if (!ins->vex.nd && ins->vex.nf)
>>>>> +    {
>>>>> +      if (opnd == 0)
>>>>> +	return OP_E (ins, v_swap_mode, sizeflag);
>>>>
>>>> There's still no testing of this use of v_swap_mode afaics.
>>>>
>>>
>>> I thought adding -Msuffix in x86-64-apx-cfcmov-intel.d and doing the
>> following tests were the tests you wanted, now it seems that I'm missing
>> something. Could you add more information? Thanks.
>>>
>>> [       ]*[a-f0-9]+:[   ]*62 f4 7d 08 42 c2[    ]+cfcmovb ax,dx
>>> [       ]*[a-f0-9]+:[   ]*62 f4 7d 0c 42 d0[    ]+cfcmovb.s ax,dx
>>> [       ]*[a-f0-9]+:[   ]*62 f4 7d 08 42 c2[    ]+cfcmovb ax,dx
>>> [       ]*[a-f0-9]+:[   ]*62 f4 7d 0c 42 d0[    ]+cfcmovb.s ax,dx
>>
>> Hmm, I overlooked that, first and foremost because I certainly did not expect
>> this to be in an Intel syntax test. The above is not really Intel syntax, and -
>> Msuffix also doesn't make a lot of sense together with -Mintel. (Read:
>> Eventually we may want to actually reject that combination, or re-purpose it
>> to make the "<xyz> PTR" printing optional when operand size is unambiguous.
>> Nevertheless I can also see the desire to have a way to express the non-default
>> encodings in Intel syntax output.)
> 
> Would you mind moving these four tests into " x86: Add {load}/{store} tests for apx instructions"?  then we can remove -Msuffix in Intel syntax tests.

That would be fine with me, yes.

Jan