[PATCH v1 2/2][Binutils] aarch64: Fix sve2p1 ld[1-4]q/st[1-4]q instructions encoding and syntax.

[Jan Beulich]

On 23.02.2024 14:59, Srinath Parvathaneni wrote:
> This patch fixes encoding and syntax for sve2p1 instructions as 
> mentioned below,
> for the issues reported here.
> https://sourceware.org/pipermail/binutils/2024-February/132408.html
> 
> 1) ld1q and st1q first register operand to accept enclosed figure braces.
> 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions to accept wrapping
>     sequence of vector registers.

The testsuite addition does not reflect this, which I think would be
relevant.

As to the spec of the 3- and 4-forms of these insns itself: Wouldn't,
for non-wrapping sequences of registers, the shorter {z<n>.q-z<m>.q}
be nice to permit at least as alternative form? And then default to
that in disassembly?

Jan

> 3) Fixes the encoding for bits 13 and 14 for ld2q's scalar plus scalar 
> encoding.
> 4) ld3q/st3q and ld4q/st4q scalar plus immediate forms accepts multiple 
> of 3 and 4
> respectively.
> 
> Regression testing for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master? Also ok to be backported to binutils-2.42 branch?
> 
> Regards,
> Srinath.