[PATCH v3 3/9] RISC-V: Add assembly support for TLSDESC.
Nelson Chu
nelson@rivosinc.com
Mon Feb 19 01:44:06 GMT 2024
On Tue, Nov 28, 2023 at 4:51 PM Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
wrote:
> gas/
> * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi,
> %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype
> renamed to percent_op_relax_only as this matcher is extended to handle
> jalr as well which is not R-type.
> (riscv_ip): Apply the percent_op_relax_only rename and update comment.
> (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to
> TLS relocation check list.
> * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation
> generation.
> opcodes/
> * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with
> %tlsdesc_call annotations.
> ---
> gas/config/tc-riscv.c | 18 +++++++++++++-----
> gas/testsuite/gas/riscv/tlsdesc.d | 22 ++++++++++++++++++++++
> gas/testsuite/gas/riscv/tlsdesc.s | 24 ++++++++++++++++++++++++
> opcodes/riscv-opc.c | 1 +
> 4 files changed, 60 insertions(+), 5 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/tlsdesc.d
> create mode 100644 gas/testsuite/gas/riscv/tlsdesc.s
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 04738d5e00c..376d2a34530 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -2113,6 +2113,7 @@ static const struct percent_op_match
> percent_op_utype[] =
> {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
> {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
> {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
> + {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20},
> {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
> {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
> {"hi", BFD_RELOC_RISCV_HI20},
> @@ -2124,6 +2125,8 @@ static const struct percent_op_match
> percent_op_itype[] =
> {"lo", BFD_RELOC_RISCV_LO12_I},
> {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
> {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
> + {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12},
> + {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12},
> {0, 0}
> };
>
> @@ -2135,8 +2138,9 @@ static const struct percent_op_match
> percent_op_stype[] =
> {0, 0}
> };
>
> -static const struct percent_op_match percent_op_rtype[] =
> +static const struct percent_op_match percent_op_relax_only[] =
> {
> + {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL},
> {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
> {0, 0}
> };
> @@ -3244,10 +3248,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> *imm_reloc = BFD_RELOC_RISCV_LO12_I;
> goto load_store;
> case '1':
> - /* This is used for TLS, where the fourth operand is
> - %tprel_add, to get a relocation applied to an add
> - instruction, for relaxation to use. */
> - p = percent_op_rtype;
> + /* This is used for TLS relocations that acts as relaxation
> + markers and do not change the instruction encoding,
> + i.e. %tprel_add and %tlsdesc_call. */
> + p = percent_op_relax_only;
>
Okay, looks good.
> goto alu_op;
> case '0': /* AMO displacement, which must be zero. */
> load_store:
> @@ -4036,6 +4040,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg
> ATTRIBUTE_UNUSED)
> case BFD_RELOC_RISCV_TPREL_LO12_I:
> case BFD_RELOC_RISCV_TPREL_LO12_S:
> case BFD_RELOC_RISCV_TPREL_ADD:
> + case BFD_RELOC_RISCV_TLSDESC_HI20:
> relaxable = true;
> /* Fall through. */
>
> @@ -4209,6 +4214,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg
> ATTRIBUTE_UNUSED)
>
> case BFD_RELOC_RISCV_CALL:
> case BFD_RELOC_RISCV_CALL_PLT:
> + case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12:
> + case BFD_RELOC_RISCV_TLSDESC_ADD_LO12:
> + case BFD_RELOC_RISCV_TLSDESC_CALL:
> relaxable = true;
> break;
>
> diff --git a/gas/testsuite/gas/riscv/tlsdesc.d
> b/gas/testsuite/gas/riscv/tlsdesc.d
> new file mode 100644
> index 00000000000..11872953d23
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/tlsdesc.d
> @@ -0,0 +1,22 @@
> +#as: -march=rv32ia
>
Probably can remove the architecture setting, so that we can test more
situations.
> +#source: tlsdesc.s
> +#readelf: -Wr
>
#objdump: -dr maye be better.
> +
> +Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 16 entries:
> + +Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
> +0+ +0+a3e +R_RISCV_TLSDESC_HI20 +0+ +sg1 \+ 0
> +0+ +0+33 +R_RISCV_RELAX + 0
> +0+4 +0+63f +R_RISCV_TLSDESC_LOAD_LO12 0+ +\.desc1 \+ 0
> +0+4 +0+33 +R_RISCV_RELAX + 0
> +0+8 +0+640 +R_RISCV_TLSDESC_ADD_LO12 0+ +\.desc1 \+ 0
> +0+8 +0+33 +R_RISCV_RELAX + 0
> +0+c +0+641 +R_RISCV_TLSDESC_CALL +0+ +\.desc1 \+ 0
> +0+c +0+33 +R_RISCV_RELAX + 0
> +0+10 +0+53e +R_RISCV_TLSDESC_HI20 +0+4 +sl1 \+ 0
> +0+10 +0+33 +R_RISCV_RELAX + 0
> +0+14 +0+83f +R_RISCV_TLSDESC_LOAD_LO12 0+10 +\.desc2 \+ 0
> +0+14 +0+33 +R_RISCV_RELAX + 0
> +0+18 +0+840 +R_RISCV_TLSDESC_ADD_LO12 0+10 +\.desc2 \+ 0
> +0+18 +0+33 +R_RISCV_RELAX +0
> +0+1c +0+841 +R_RISCV_TLSDESC_CALL +0+10 +\.desc2 \+ 0
> +0+1c +0+33 +R_RISCV_RELAX +0
[ ] means [space+tab]
0+000 <_start>:
[ ]+0:[ ]+[0-9a-f]+[ ]+auipc[ ]+a0,0x0
[ ]+0:[ ]+R_RISCV_TLSDESC_HI20[ ]+sg1
[ ]+0:[ ]+R_RISCV_RELAX[ ]+0
...
> diff --git a/gas/testsuite/gas/riscv/tlsdesc.s
> b/gas/testsuite/gas/riscv/tlsdesc.s
> new file mode 100644
> index 00000000000..15468d5f947
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/tlsdesc.s
> @@ -0,0 +1,24 @@
> + .section .tbss,"awT",@nobits
> + .global sg1
> +sg1:
> + .zero 4
> +sl1:
> + .zero 4
> +
> + .text
> + .globl _start
> + .type _start,@function
> +_start:
> +.desc1:
> + auipc a0, %tlsdesc_hi(sg1)
> + lw t0, %tlsdesc_load_lo(.desc1)(a0)
> + addi a0, a0, %tlsdesc_add_lo(.desc1)
> + jalr t0, t0, %tlsdesc_call(.desc1)
> +
> +.desc2:
> + auipc a0, %tlsdesc_hi(sl1)
> + lw t0, %tlsdesc_load_lo(.desc2)(a0)
> + addi a0, a0, %tlsdesc_add_lo(.desc2)
> + jalr t0, t0, %tlsdesc_call(.desc2)
> +
> + ret
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bf19978e025..edaf4b0c8b5 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -372,6 +372,7 @@ const struct riscv_opcode riscv_opcodes[] =
> {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA <<
> OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR,
> MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR },
> {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR,
> match_opcode, INSN_JSR },
> +{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR,
> MASK_JALR|MASK_IMM, match_opcode, INSN_JSR },
> {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR,
> match_opcode, INSN_JSR },
> {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J,
> match_opcode, INSN_ALIAS|INSN_BRANCH },
> {"j", 0, INSN_CLASS_I, "a", MATCH_JAL,
> MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
> --
> 2.43.0
>
>
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