[PATCH v2] x86: adjust which Dwarf2 register numbers to use

[Jan Beulich]

Consumers can't know which execution mode is in effect for a certain
piece of code; they can only go from object file properties. Hence which
register numbers to encode ought to depend solely on object file type.
---
x86_cie_data_alignment, independent of this change, likely needs
adjusting as flag_code changes.

The COFF/PE setting of x86_dwarf2_return_column looks bogus as well: 32
is already in use for %xmm15 for 64-bit. Commit ca19b261ecc3 sadly has
no explanation at all. Nor did it adjust objdump accordingly. Given that
the author has moved on (couldn't find an applicable email address), I'm
inclined to simply revert that change. If anything a proper complete set
of Windows register number mappings (wherever those are formally
documented) would need putting in place.
---
v2: Also adjust md_begin().

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3276,7 +3276,7 @@ md_begin (void)
       operand_chars[(unsigned char) *p] = *p;
   }
 
-  if (flag_code == CODE_64BIT)
+  if (object_64bit)
     {
 #if defined (OBJ_COFF) && defined (TE_PE)
       x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
@@ -5409,7 +5409,7 @@ ginsn_dw2_regnum (const reg_entry *ireg)
   if (ireg->reg_num == RegIP || ireg->reg_num == RegIZ)
     return GINSN_DW2_REGNUM_RSI_DUMMY;
 
-  dwarf_reg = ireg->dw2_regnum[flag_code >> 1];
+  dwarf_reg = ireg->dw2_regnum[object_64bit];
 
   if (dwarf_reg == Dw2Inval)
     {
@@ -17461,7 +17461,7 @@ tc_x86_parse_to_dw2regnum (expressionS *
       if ((addressT) exp->X_add_number < i386_regtab_size)
 	{
 	  exp->X_add_number = i386_regtab[exp->X_add_number]
-			      .dw2_regnum[flag_code >> 1];
+			      .dw2_regnum[object_64bit];
 	  if (exp->X_add_number != Dw2Inval)
 	    exp->X_op = O_constant;
 	}