[PATCH] arc: Put DBNZ instruction to a separate class

[Claudiu Zissulescu Ianculescu]

Hi Yuriy,

Looks good to me.

Thank you for your contribution,
Claudiu

On Fri, Feb 9, 2024 at 4:27 PM Yuriy Kolerov <Yuriy.Kolerov@synopsys.com> wrote:
>
> DBNZ instruction decrements its source register operand, and if
> the result is non-zero it branches to the location defined by a signed
> half-word displacement operand.
>
> DBNZ instruction is in BRANCH class as other branch instrucitons
> like B, Bcc, etc. However, DBNZ is the only branch instruction
> that stores a branch offset in the second operand. Thus it must
> be placed in a distinct class and treated differently.
>
> For example, current logic of arc_insn_get_branch_target in GDB
> assumes that a branch offset is always stored in the first operand
> for BRANCH class and it's wrong for DBNZ.
>
> Signed-off-by: Yuriy Kolerov <ykolerov@synopsys.com>
> ---
>  gas/config/tc-arc.c  | 1 +
>  include/opcode/arc.h | 1 +
>  opcodes/arc-dis.c    | 1 +
>  opcodes/arc-tbl.h    | 2 +-
>  4 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
> index bf2f5e0fd4c..a76d3a7eee8 100644
> --- a/gas/config/tc-arc.c
> +++ b/gas/config/tc-arc.c
> @@ -114,6 +114,7 @@ enum arc_rlx_types
>                                   || (op)->insn_class == BBIT0          \
>                                   || (op)->insn_class == BBIT1          \
>                                   || (op)->insn_class == BI             \
> +                                 || (op)->insn_class == DBNZ           \
>                                   || (op)->insn_class == EI             \
>                                   || (op)->insn_class == ENTER          \
>                                   || (op)->insn_class == JLI            \
> diff --git a/include/opcode/arc.h b/include/opcode/arc.h
> index fe3278ab706..67362431800 100644
> --- a/include/opcode/arc.h
> +++ b/include/opcode/arc.h
> @@ -52,6 +52,7 @@ typedef enum
>    BRANCH,
>    BRCC,
>    CONTROL,
> +  DBNZ,
>    DIVREM,
>    DMA,
>    DPI,
> diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
> index dbcd0dbd7f8..68b1c2043cc 100644
> --- a/opcodes/arc-dis.c
> +++ b/opcodes/arc-dis.c
> @@ -979,6 +979,7 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
>      case BI:
>      case BIH:
>      case BRCC:
> +    case DBNZ:
>      case EI:
>      case JLI:
>      case JUMP:
> diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
> index b90413de7ef..40184ab76be 100644
> --- a/opcodes/arc-tbl.h
> +++ b/opcodes/arc-tbl.h
> @@ -3656,7 +3656,7 @@
>  { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
>
>  /* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
> -{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
> +{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DBNZ, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
>
>  /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
>  { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},
> --
> 2.34.1
>