[PATCH v4 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions

[Nelson Chu]

On Tue, Jan 16, 2024 at 6:56 PM Mary Bennett <mary.bennett@embecosm.com>
wrote:

> v3 -> v4:
>  * Remove trailing white space
>  * Since the XCVbi instructions uses a relocation, linker tests were
>    added. I think it best if we keep them just to prove that the CORE-V
>    instructions are correct.
>

 I don't think keeping the ld testcase is necessary since you don't add any
new relocation.  The cv.beqimm uses R_RISCV_BRANCH, and only changes the
assembler code, so adding an assembler testcase with readelf or objdump -dr
should be the right way to go.  Unless the cv.beqimm changes the
R_RISCV_BRANCH behavior and need a new relocation, otherwise no ld testcase
required.

Thanks
Nelson
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://sourceware.org/pipermail/binutils/attachments/20240202/c0efcd7a/attachment.htm>