[PATCH v3] Support Intel AMX-TRANSPOSE

[Jan Beulich]

On 24.12.2024 10:01, Haochen Jiang wrote:
> @@ -10750,15 +10752,24 @@ process_operands (void)
>        unsigned int op, extra;
>        const reg_entry *first;
>  
> -      /* The second operand must be {x,y,z}mmN. */
> -      gas_assert (i.operands == 3 && i.types[1].bitfield.class == RegSIMD);
> +      /* The second operand must be {x,y,z,t}mmN */

As you touch this comment, please
- don't purge the full stop,
- take the opportunity and add the missing 2nd blank at the end.

> +      gas_assert ((i.operands == 2 || i.operands == 3)
> +		  && i.types[1].bitfield.class == RegSIMD);
>  
> -      switch (i.types[2].bitfield.class)
> +      switch (i.types[i.operands - 1].bitfield.class)
>  	{
>  	case RegSIMD:
> -	  /* AVX512-{4FMAPS,4VNNIW} operand 2: N must be a multiple of 4. */
>  	  op = 1;
> -	  extra = 3;
> +	  if (i.types[i.operands - 1].bitfield.tmmword)

There wouldn't be anything wrong with using the cheaper i.types[1] here, or
even simply "i.operands == 2", would it?

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3210,6 +3210,26 @@ tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
>  
>  tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
>  
> +<z:opc, z0:, z1:66>

Why "opc" when what you're templatizing is the (embedded) prefix? Please use
"pfx" in such cases, as we do elsewhere. That'll then also ...

> +<loc:opc, $t:0x0, t1:0x1>
> +
> +t2rpntlvw<z><loc>, 0x<z:opc>6e | <loc:opc>, APX_F(AMX_TRANSPOSE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM }

... eliminate the double use of "opc" here, which may end up being slightly
confusing.

Okay with respective adjustments.

Jan