[PATCH v1] x86: Support ZHAOXIN padlock instructions

[Jan Beulich]

On 24.12.2024 02:59, Mayshao-oc wrote:
>       Thanks for your review, I change the patch according to your comments. 
>       As to the "You cannot tie the new insns to the same old PadLock CPU feature", I  agree with you, new insns need new cpuid bit to indicate their present.

Yet you still key all new insns to PadLock?

As said before - please don't replace existing references to VIA by ones
to Zhaoxin. And please don't make unrelated changes to the opcode table.
I'm pretty sure I said before that I don't see why you move around some
of the entries.

Please also stick to singular when renaming MONTMUL_Fixup(). All other
such functions are named xyz_Fixup() as well, iirc.

Jan