[PATCH] aarch64: Make VGx4 symbol mandatory for fvdotb and fvdott

[Andrew Carlotti]

Add tests for this, and update the existing fvdotb and fvdott tests to
include the VGx4 symbol so that they continue to test for the intended
errors.


Ok for master?


diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
index bd25bb34b2ff50ba092f1a6cd9589e961400bd33..30e987da7703fee9752044b34b66607b5c35c626 100644
--- a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
@@ -73,15 +73,18 @@
 [^:]*:84: Error: start register out of range at operand 2 -- `fvdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
 [^:]*:85: Error: z0-z15 expected at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
 [^:]*:86: Error: register element index out of range 0 to 7 at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
-[^:]*:88: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:89: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:90: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdotb za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:91: Error: start register out of range at operand 2 -- `fvdotb za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:92: Error: z0-z15 expected at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:93: Error: register element index out of range 0 to 3 at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
-[^:]*:95: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:96: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:97: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdott za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:98: Error: start register out of range at operand 2 -- `fvdott za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:99: Error: z0-z15 expected at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:100: Error: register element index out of range 0 to 3 at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:88: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w7,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:89: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w12,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:90: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdotb za\.s\[w8,8,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:91: Error: start register out of range at operand 2 -- `fvdotb za\.s\[w8,0,VGx4\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:92: Error: z0-z15 expected at operand 3 -- `fvdotb za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:93: Error: register element index out of range 0 to 3 at operand 3 -- `fvdotb za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:95: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w7,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:96: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w12,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:97: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdott za\.s\[w8,8,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:98: Error: start register out of range at operand 2 -- `fvdott za\.s\[w8,0,VGx4\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:99: Error: z0-z15 expected at operand 3 -- `fvdott za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:100: Error: register element index out of range 0 to 3 at operand 3 -- `fvdott za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[4\]'
+
+[^:]*:102: Error: operand 1 must have a vector group size of 4 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:103: Error: operand 1 must have a vector group size of 4 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s
index 508bd79e538078ad881a3dec6a2f11633b4938f7..241f47d3ee8e36b6443ca677dc3fdb0aab3f70a3 100644
--- a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s
@@ -85,16 +85,19 @@ fvdot za.h[w8, 0], {z1.b-z2.b}, z0.b[0]
 fvdot za.h[w8, 0], {z0.b-z1.b}, z16.b[0]
 fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[8]
 
-fvdotb za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
-fvdotb za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
-fvdotb za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
-fvdotb za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
-fvdotb za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
-fvdotb za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+fvdotb za.s[w7, 0, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w12, 0, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 8, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], {z1.b-z2.b}, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], {z0.b-z1.b}, z16.b[0]
+fvdotb za.s[w8, 0, VGx4], {z0.b-z1.b}, z0.b[4]
 
-fvdott za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
-fvdott za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
-fvdott za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
-fvdott za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
-fvdott za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
-fvdott za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+fvdott za.s[w7, 0, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w12, 0, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 8, VGx4], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 0, VGx4], {z1.b-z2.b}, z0.b[0]
+fvdott za.s[w8, 0, VGx4], {z0.b-z1.b}, z16.b[0]
+fvdott za.s[w8, 0, VGx4], {z0.b-z1.b}, z0.b[4]
+
+fvdotb za.s[w8, 0], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 0], {z0.b-z1.b}, z0.b[0]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 172c9a44845b77d29ee808971c96de72e94f7f71..d17275d1b7455b5bcec304be218d2e2969f1c762 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6883,8 +6883,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SME_F8F16_INSNC("fmopa", 0x80a00008, 0xffe0001e, sme_misc, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMBB, 0, 0),
   SME_F8F32_INSNC("fmopa", 0x80a00000, 0xffe0001c, sme_misc, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
   SME_F8F16_INSNC("fvdot", 0xc1d01020, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (2), 0),
-  SME_F8F32_INSNC("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0),
-  SME_F8F32_INSNC("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0),
+  SME_F8F32_INSNC("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0),
+  SME_F8F32_INSNC("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0),
 
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };