[PATCH 0/2] RISC-V: Fix disassembly for dynamic libraries

[Marek Pikuła]

This patchset improves experience for code disassembly in GDB for RISC-V, when
interacting with dynamically linked libraries.

For example, a binary might be built for a generic `rv64gc` target, but a
library that the binary loads might be built for `rv64gcv`. In that case, when
only `abfd` provides information to disassembler, the vector instructions don't
get disassembled correctly (and are shown as generic `.insn`). With this
patchset, the disassembler checks which object file is in scope. Thus, it
adjusts the output to the ISA subset present in `Tag_RISCV_arch` from the object
file in the current scope.

While this change is directed mainly towards GDB, its main focus is libopcodes,
thus this patchset is sent both to GDB and binutils mailing lists.

Marek Pikuła (2):
  opcodes: Add bfd handles to disassemble_info
  RISC-V: Use obfd for disassembly instead of abfd

 binutils/objdump.c            |  3 +-
 gdb/arch-utils.c              |  2 +-
 gdb/disasm.c                  | 14 +++++++++
 gprofng/libcollector/unwind.c |  9 ++++++
 gprofng/src/Disasm.cc         | 12 ++++++--
 include/dis-asm.h             | 20 +++++++------
 opcodes/arc-dis.c             | 31 ++++++++------------
 opcodes/cris-dis.c            |  9 +++++-
 opcodes/csky-dis.c            | 54 +++++++++++++++++------------------
 opcodes/dis-init.c            | 11 ++++++-
 opcodes/disassemble.c         | 13 ++++-----
 opcodes/disassemble.h         |  7 ++---
 opcodes/riscv-dis.c           | 49 ++++++++++++++-----------------
 opcodes/rl78-dis.c            | 12 ++++++--
 sim/arm/wrapper.c             |  3 +-
 sim/common/sim-trace.c        |  4 +--
 sim/cris/sim-if.c             |  9 +++---
 sim/m32c/trace.c              |  1 +
 sim/rl78/trace.c              |  3 +-
 sim/rx/trace.c                |  1 +
 20 files changed, 156 insertions(+), 111 deletions(-)


base-commit: 7336a8977d81b7b8c00f2e8ccb8a084afb33b19a
--
2.47.0