[PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
Andrew Carlotti
andrew.carlotti@arm.com
Fri Aug 16 16:20:17 GMT 2024
On Fri, Jul 12, 2024 at 05:35:34PM +0100, Srinath Parvathaneni wrote:
>
> This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls,
> which are available on passing command line flags +sme-f16f16 and the
> spec is available here[1].
> [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
> ---
...
> diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.d b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
> new file mode 100644
> index 00000000000..0cf05f2b320
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
> @@ -0,0 +1,98 @@
> +#name: Test of FEAT_SME_F16F16 fmla and fmls instructions.
> +#as: -march=armv9.4-a+sme-f16f16
This could instead use -march=armv8-a+sme-f16f16 to demonstrate that the
instructions aren't gated behind any other feature enabled by armv9.4-a.
> +#objdump: -dr
> +
> +[^:]+: file format .*
> +
> +
> +[^:]+:
> +
> +[^:]+:
> +.*: c1101000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1107000 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1101007 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c11013c0 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
> +.*: c11f1000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
> +.*: c1101c08 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c11f7fcf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
> +.*: c1101c0b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c1109000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c110f000 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109007 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109380 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
> +.*: c11f9000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
> +.*: c1109c08 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c11fff8f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
> +.*: c1109c0b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c1201c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1207c00 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201c07 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201fe0 fmla za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
> +.*: c12f1c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c12f7fc7 fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
> +.*: c12f1c03 fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c1301c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1307c00 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301c07 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301fe0 fmla za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
> +.*: c13f1c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c13f7f87 fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
> +.*: c13f1c03 fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c1a01008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a07008 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a0100f fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a013c8 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
> +.*: c1be1008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1be73cf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
> +.*: c1be100b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1a11008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a17008 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a1100f fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a11388 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
> +.*: c1bd1008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1bd738f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
> +.*: c1bd100b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1101010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1107010 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1101017 fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c11013d0 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
> +.*: c11f1010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
> +.*: c1101c18 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c11f7fdf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
> +.*: c1101c1b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c1109010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c110f010 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109017 fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109390 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
> +.*: c11f9010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
> +.*: c1109c18 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c11fff9f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
> +.*: c1109c1b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c1201c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1207c08 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201c0f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201fe8 fmls za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
> +.*: c12f1c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c12f7fcf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
> +.*: c12f1c0b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c1301c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1307c08 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301c0f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301fe8 fmls za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
> +.*: c13f1c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c13f7f8f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
> +.*: c13f1c0b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c1a01018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a07018 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a0101f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a013d8 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
> +.*: c1be1018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1be73df fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
> +.*: c1be101b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1a11018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a17018 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a1101f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a11398 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
> +.*: c1bd1018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1bd739f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
> +.*: c1bd101b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.s b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
> new file mode 100644
> index 00000000000..86e39bde65a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
> @@ -0,0 +1,105 @@
> +/* FMLA (multiple and indexed vector). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
> +fmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
The index is split across non-contiguous bits in the encoding, so it's
important to make sure that we don't get the bits in the wrong order by mixing
up the order of the fields. One extra test would suffice (for each opcode
table entry); any index value that isn't 0 or 7 (together with the existing 0
and 7 tests) would be enough to show that the field order is correct.
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
> +fmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
> +
> +/* FMLA (multiple and single vector). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
> +fmla za.h[w8, 3], {z0.h - z1.h}, z15.h
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
> +fmla za.h[w8, 3], {z0.h - z3.h}, z15.h
> +
> +/* FMLA (multiple vectors). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
> +fmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
> +fmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
> +
> +/* FMLS (multiple and indexed vector). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
> +fmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
> +fmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
> +
> +/* FMLS (multiple and single vector). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
> +fmls za.h[w8, 3], {z0.h - z1.h}, z15.h
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
> +fmls za.h[w8, 3], {z0.h - z3.h}, z15.h
> +
> +/* FMLS (multiple vectors). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
> +fmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
> +fmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index cd8c8257aec..a67ab1d84da 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -6699,6 +6699,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> /* SME2.1 half-precision floating-point instructions. */
> SME_F16F16_INSN("fmopa", 0x81800008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
> SME_F16F16_INSN("fmops", 0x81800018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
> + SME_F16F16_INSN("fmla", 0xc1101000, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
> + SME_F16F16_INSN("fmla", 0xc1109000, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
> + SME_F16F16_INSN("fmla", 0xc1201c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmla", 0xc1301c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmla", 0xc1a01008, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmla", 0xc1a11008, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmls", 0xc1101010, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
> + SME_F16F16_INSN("fmls", 0xc1109010, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
> + SME_F16F16_INSN("fmls", 0xc1201c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmls", 0xc1301c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmls", 0xc1a01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmls", 0xc1a11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
>
> /* SVE2p1 Instructions. */
> SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
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