[RFC] RISC-V: Add support for Profiles RVA/B23.

[Jiawei]

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], 
which depend on the base RISC-V Profiles support[2].

[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://sourceware.org/pipermail/binutils/2024-August/136190.html

bfd/ChangeLog:

	* elfxx-riscv.c: New Profiles.

gas/ChangeLog:

	* NEWS: Add RISC-V Profiles RV23A/B. 
	* testsuite/gas/riscv/attribute-17.d: New test.
	* testsuite/gas/riscv/attribute-18.d: New test.

---
 bfd/elfxx-riscv.c                      | 16 ++++++++++++++++
 gas/NEWS                               |  2 ++
 gas/testsuite/gas/riscv/attribute-17.d |  6 ++++++
 gas/testsuite/gas/riscv/attribute-18.d |  6 ++++++
 4 files changed, 30 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/attribute-17.d
 create mode 100644 gas/testsuite/gas/riscv/attribute-18.d

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 96ab82fec5f..877f7f38c87 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1298,6 +1298,22 @@ static struct riscv_profiles riscv_profiles_table[] =
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+     'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+     extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+     'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+     extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles.  */
 
   /* Terminate the list.  */
diff --git a/gas/NEWS b/gas/NEWS
index e0b0aaf78c6..57eee56b475 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -4,6 +4,8 @@
 
 * Add support for RISC-V Profiles RV20/22.
 
+* Add support for RISC-V Profiles RV23A/B.
+
 Changes in 2.43:
 
 * Add support for LoongArch .option for fine-grained control of assembly
diff --git a/gas/testsuite/gas/riscv/attribute-17.d b/gas/testsuite/gas/riscv/attribute-17.d
new file mode 100644
index 00000000000..e2142d521ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-17.d
@@ -0,0 +1,6 @@
+#as: -march=RVA23U64
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/attribute-18.d b/gas/testsuite/gas/riscv/attribute-18.d
new file mode 100644
index 00000000000..f08e7dfc86e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-18.d
@@ -0,0 +1,6 @@
+#as: -march=RVB23U64
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
-- 
2.25.1