[PATCH v1 1/1] opcodes: microblaze: Add new bit-field instructions

[Nick Clifton]

Hi Neal,

> This patches adds new bsefi and bsifi instructions.
> BSEFI- The instruction shall extract a bit field from a
> register and place it right-adjusted in the destination register.
> The other bits in the destination register shall be set to zero.
> BSIFI- The instruction shall insert a right-adjusted bit field
> from a register at another position in the destination register.
> The rest of the bits in the destination register shall be unchanged.
> 
> Further documentation of these instructions can be found here:
> https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
> 
> This patch has been tested for years of AMD Xilinx Yocto
> releases as part of the following patch set:
> 
> https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils
> 
> Signed-off-by:nagaraju <nagaraju.mekala@amd.com>
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
>   gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
>   opcodes/microblaze-dis.c   | 16 +++++++++
>   opcodes/microblaze-opc.h   | 12 ++++++-
>   opcodes/microblaze-opcm.h  |  6 +++-
>   4 files changed, 102 insertions(+), 3 deletions(-)

Patch approved, please apply.

But please may I also request a follow up patch to add a test
for these new instructions to the assembler testsuite, eg in
gas/testsuite/gas/microblaze/allinsn.[sd],

Cheers
   Nick