[PATCH v3 1/3] RISC-V: Remove RV64E conflict
Tsukasa OI
research_trasio@irq.a4lg.com
Tue Sep 5 09:08:35 GMT 2023
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Since RV32E *and* RV64E are ratified, RV64E is no longer invalid.
This commit removes a restriction that prevents making base ISA with
reduced GPRs with XLEN > 32.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E
conflict since the ratified 'E' base ISAs include RV64E.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-base-02.d: Removed.
* testsuite/gas/riscv/march-fail-base-02.l: Removed.
---
bfd/elfxx-riscv.c | 7 -------
gas/testsuite/gas/riscv/march-fail-base-02.d | 3 ---
gas/testsuite/gas/riscv/march-fail-base-02.l | 2 --
3 files changed, 12 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d
delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e642a05fe5b8..4553075735f8 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1946,13 +1946,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
int xlen = *rps->xlen;
bool no_conflict = true;
- if (riscv_lookup_subset (rps->subset_list, "e", &subset)
- && xlen > 32)
- {
- rps->error_handler
- (_("rv%d does not support the `e' extension"), xlen);
- no_conflict = false;
- }
if (riscv_subset_supports (rps, "e")
&& riscv_subset_supports (rps, "h"))
{
diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d
deleted file mode 100644
index cfe085ab21aa..000000000000
--- a/gas/testsuite/gas/riscv/march-fail-base-02.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64e
-#source: empty.s
-#error_output: march-fail-base-02.l
diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l
deleted file mode 100644
index 52fee96af368..000000000000
--- a/gas/testsuite/gas/riscv/march-fail-base-02.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*Assembler messages:
-.*Error: rv64 does not support the `e' extension
--
2.42.0
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