[PATCH v2 3/3] x86: support AVX10.1 vector size restrictions

[Jan Beulich]

On 05.09.2023 10:11, Jiang, Haochen wrote:
>> Recognize "/<number>" suffixes on both -march=+avx10.1 and the
>> corresponding .arch directive, setting an upper bound on the vector size
>> that insns may use. Such a restriction can be reset by setting a new base
>> architecture, by using a suffix-less form, by disabling AVX10, or by
>> enabling any other VEX/EVEX-based vector extension.
> 
> Currently in GCC community, they are asking for an option -m[no-]evex512
> to enable/disable 512 bit register and 64 bit mask register. I will add a similar
> option in binutils afterwards.
> 
> Also, they are not willing to introduce actual -mavx10.1-256/512. Therefore,
> it might become a little problematic to introduce them in binutils only.

I don't see a problem with compiler and assembler supporting somewhat
diverging options. In fact we already have examples, like -m64 vs --64.

> But since there will be finally -mavx10.2-256/512, the current code change
> for attribute is always ok.

Good.

Jan