[PATCH 5/5] x86: support AVX10.1 vector size restrictions

[Jiang, Haochen]

> >>
> >> AVX10 spec only has
> >>
> >> Quadword opmask instructions will only be supported on processors
> >> supporting vector lengths of 512 bits.
> >>
> >> It doesn't say anything about 32-bit mask.   32-bit mask can be useful
> >> even with 16 byte vector.
> 
> How's that any different for 64-bit mask with 32-byte vector?
> 
> > The concern form my side is if there is an extreme case that overloads
> > registers, we might need to spill 32-bit register to 32-bit mask
> > register in the compiler.
> 
> How's that any different for spilling of 64-bit registers?
>

In GCC, under 256 bit mode, we will ban them. But since there is no definition
for 128 bit mode in GCC for a long time, it will leave some space of undefined.

Actually, the cost for that spill is really high. So it should be little concern, not a
blocking issue.

Thx,
Haochen