[PATCH v1 1/1] opcodes: microblaze: Fix bit masking bug

[Michael Eager]

On 10/19/23 04:37, Neal Frager wrote:
> There is currently a bug in the bit masking for the barrel shift
> instructions because the bit mask is not including all of the
> register bits which must be zero.  With this patch, the disassembler
> can be sure that the 32-bit value is indeed a barrel shift instruction
> and not a data value in memory.
> 
> This fix can be verified by assembling and disassembling the following:
> 
> 	.text
> 	.long 0x65005f5f
> 
> With this patch, the bug is fixed, and the objdump will know that
> 0x65005f5f is not a barrel shift instruction.
> 
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
>   gas/testsuite/gas/microblaze/allinsn.d |  4 ++--
>   opcodes/microblaze-dis.c               |  4 ++--
>   opcodes/microblaze-opc.h               | 11 +++++++----
>   3 files changed, 11 insertions(+), 8 deletions(-)

Committed.

-- 
Michael Eager