[PATCH v4 1/1] opcodes: microblaze: Add new bit-field instructions

[Frager, Neal]

Hi Michael,

> static char *
>  get_field_rfsl (struct string_buf *buf, long instr)  { @@ -426,6 +441,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
> 	  break;
> 	  /* For mbar 16 or sleep insn.  */
> 	case INST_TYPE_NONE:
> +	  break;
> +	  /* For bit field insns.  */
> +	case INST_TYPE_RD_R1_IMM5_IMM5:
> +	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, 
> +inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), 
> +get_field_imm5 (&buf, inst));

I missed this line which is >80 chars.  Please review only v5 of this patch which fixes this.

> 	  break;
> 	  /* For tuqula instruction */
> 	case INST_TYPE_RD:

Best regards,
Neal Frager
AMD