[PATCH 0/2] RISC-V: a little more macro insn handling adjusting

[Jan Beulich]

On 22.11.2023 01:39, Andrew Waterman wrote:
> On Tue, Nov 21, 2023 at 4:26 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Fri, 17 Nov 2023 02:18:12 PST (-0800), jbeulich@suse.com wrote:
>>> On 03.11.2023 13:55, Jan Beulich wrote:
>>>> 1: disallow x0 with certain macro-insns
>>>> 2: reduce redundancy in sign/zero extension macro insn handling
>>>
>>> Not hearing anything back kind of suggests no objections. I'll commit
>>> these two patches at the end of next week unless I hear back earlier.
>>
>> Sorry for being slow here.  I don't really have a strong feeling either
>> way: having x0 in these macros results in legal instructions, even if
>> they're probably semanticly useless (I suppose one can map address 0,
>> but that's probably a bad idea).
> 
> There are legitimate use.cases for using x0 as a base register, e.g.
> the debug ROM code which takes advantage of the fact that the debug
> module registers live at the low addresses:
> https://github.com/riscv-software-src/riscv-isa-sim/blob/4841ad0238f0b71ca86fb28974765495cc0c34a9/debug_rom/debug_rom.S#L35
> 
> That use case isn't broken by this change, since it uses a bona fide
> instruction, not a macro.  I only mention it to point out that we
> wouldn't want to ban use of x0 as a base address in non-macro
> contexts.

Right, we had that discussion a year or two ago. But as you imply, I
didn't see that extending to these macros insns.

Jan