[PATCH v2 0/8] Support Intel APX EGPR

[Jan Beulich]

On 07.11.2023 02:53, Cui, Lili wrote:
>>>> Subject: Re: [PATCH v2 0/8] Support Intel APX EGPR
>>>>
>>>> On 06.11.2023 15:20, Cui, Lili wrote:
>>> There are some VEX instructions that support NF, their vex and evex cannot
>> be merged.
>>
>> Why not?
>>
> Like bextr, new EVEX table has NF tag, I think we cannot merge them.
> 
> bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVVSrc|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
> bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVVSrc|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }

NF is no different than, say, SAE (which didn't get in the way of folding VEX
and EVEX templates). It's a(nother) reliable indication that EVEX encoding is
going to be needed.

Jan