[RFC PATCH] RISC-V: Support Zacas extension.

[Jan Beulich]

On 12.05.2023 05:44, Gianluca Guida wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1053,6 +1053,20 @@ const struct riscv_opcode riscv_opcodes[] =
>   {"sm3p0",    0, INSN_CLASS_ZKSH,    "d,s",    MATCH_SM3P0, MASK_SM3P0, 
> match_opcode, 0 },
>   {"sm3p1",    0, INSN_CLASS_ZKSH,    "d,s",    MATCH_SM3P1, MASK_SM3P1, 
> match_opcode, 0 },
>   +/* Zacas instructions.  */
> +{"amocas.w",         0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, 
> MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amocas.d",         0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, 
> MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amocas.q",        64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q, 
> MASK_AMOCAS_Q|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },

There are constraints on the usable registers for the 2*XLEN operations.
You neither reject invalid input during assembly, nor do you flag bad
encodings as such during disassembly. (Both aspects would also want to
have respective testcases, imo.)

As an aside please be aware that your patch came through slightly
mangled. If you can't change your mailer suitably, please attach the
patch (besides inlining it, which makes commenting easier).

Jan