[PATCH 4/4] RISC-V: Add Zcd extension testcases.

[Jiawei]

Add Zcd extension testcases, Zcd only compress double float
instructions.

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

gas/ChangeLog:

        * testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.d: New test.
        * testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.l: New test.
        * testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.s: New test.
        * testsuite/gas/riscv/zc-zcd-fld.d: New test.
        * testsuite/gas/riscv/zc-zcd-fld.s: New test.
        * testsuite/gas/riscv/zc-zcd-fsd.d: New test.
        * testsuite/gas/riscv/zc-zcd-fsd.s: New test

---
 .../gas/riscv/zc-zcd-fld-fsd-fail-march.d        |  3 +++
 .../gas/riscv/zc-zcd-fld-fsd-fail-march.l        | 13 +++++++++++++
 .../gas/riscv/zc-zcd-fld-fsd-fail-march.s        | 15 +++++++++++++++
 gas/testsuite/gas/riscv/zc-zcd-fld.d             | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zc-zcd-fld.s             |  8 ++++++++
 gas/testsuite/gas/riscv/zc-zcd-fsd.d             | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zc-zcd-fsd.s             |  8 ++++++++
 7 files changed, 79 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fld.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fld.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fsd.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcd-fsd.s

diff --git a/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.d b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.d
new file mode 100644
index 00000000000..ed8ff7d1a09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zc-zcd-fld-fsd-fail-march.s
+#error_output: zc-zcd-fld-fsd-fail-march.l
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.l b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.l
new file mode 100644
index 00000000000..2a36dc9ffb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fld fa0,0\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,64\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,128\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,0\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,64\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,128\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,0\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,64\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,128\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,0\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,64\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,128\(sp\)', extension `d' required
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.s b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.s
new file mode 100644
index 00000000000..6c772a82e9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fld-fsd-fail-march.s
@@ -0,0 +1,15 @@
+# Absence of zcd or dc march option disables all zcd
+target:
+	# ZCD only compress double float instructions
+        fld fa0, 0(a0)
+        fld fa0, 64(a0)
+        fld fa0, 128(a0)
+        fld fa0, 0(sp)
+        fld fa0, 64(sp)
+        fld fa0, 128(sp)
+        fsd fa0, 0(a0)
+        fsd fa0, 64(a0)
+        fsd fa0, 128(a0)
+        fsd fs2, 0(sp)
+        fsd fs2, 64(sp)
+        fsd fs2, 128(sp)
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fld.d b/gas/testsuite/gas/riscv/zc-zcd-fld.d
new file mode 100644
index 00000000000..1ea287ca019
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fld.d
@@ -0,0 +1,16 @@
+#as: -march=rv64ifd_zcd
+#source: zc-zcd-fld.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+2108[ 	]+c.fld[ 	]+fa0,0\(a0\)
+[ 	]+2:[ 	]+2128[ 	]+c.fld[ 	]+fa0,64\(a0\)
+[ 	]+4:[ 	]+2148[ 	]+c.fld[ 	]+fa0,128\(a0\)
+[ 	]+6:[ 	]+2502[ 	]+c.fldsp[ 	]+fa0,0\(sp\)
+[ 	]+8:[ 	]+2506[ 	]+c.fldsp[ 	]+fa0,64\(sp\)
+[ 	]+a:[ 	]+250a[ 	]+c.fldsp[ 	]+fa0,128\(sp\)
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fld.s b/gas/testsuite/gas/riscv/zc-zcd-fld.s
new file mode 100644
index 00000000000..b185f5f6763
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fld.s
@@ -0,0 +1,8 @@
+target:
+	# ZCD only compress double float instructions
+        fld fa0, 0(a0)   #CM
+        fld fa0, 64(a0)   #CM
+        fld fa0, 128(a0) #CM
+        fld fa0, 0(sp)   #CK
+        fld fa0, 64(sp)   #CK
+        fld fa0, 128(sp) #CK
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fsd.d b/gas/testsuite/gas/riscv/zc-zcd-fsd.d
new file mode 100644
index 00000000000..76879b82f13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fsd.d
@@ -0,0 +1,16 @@
+#as: -march=rv64ifd_zcd
+#source: zc-zcd-fsd.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+a108[ 	]+c.fsd[ 	]+fa0,0\(a0\)
+[ 	]+2:[ 	]+a128[ 	]+c.fsd[ 	]+fa0,64\(a0\)
+[ 	]+4:[ 	]+a148[ 	]+c.fsd[ 	]+fa0,128\(a0\)
+[ 	]+6:[ 	]+a04a[ 	]+c.fsdsp[ 	]+fs2,0\(sp\)
+[ 	]+8:[ 	]+a0ca[ 	]+c.fsdsp[ 	]+fs2,64\(sp\)
+[ 	]+a:[ 	]+a14a[ 	]+c.fsdsp[ 	]+fs2,128\(sp\)
diff --git a/gas/testsuite/gas/riscv/zc-zcd-fsd.s b/gas/testsuite/gas/riscv/zc-zcd-fsd.s
new file mode 100644
index 00000000000..53a77174b15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcd-fsd.s
@@ -0,0 +1,8 @@
+target:
+	# ZCD only compress double float instructions
+        fsd fa0, 0(a0)
+        fsd fa0, 64(a0)
+        fsd fa0, 128(a0)
+        fsd fs2, 0(sp)
+        fsd fs2, 64(sp)
+        fsd fs2, 128(sp)
-- 
2.25.1