[RFC PATCH v2] RISC-V: Support Zacas extension.

[Gianluca Guida]

Jan,

Thanks for taking the time to review this.

On Thu, Jun 01, 2023 at 11:03:34AM +0200, Jan Beulich wrote:
> On 31.05.2023 18:28, Gianluca Guida wrote:
> >  Changes from v1:
> >   - Added check for even registers in AMOCAS.D/32 and AMOCAS.Q
> >   - Added fail tests for odd registers.
>
> Okay, that's the assembler side testing. How about the disassembler
> side? (Note that I'm not a RISC-V maintainer, so my view here may not
> count at all.)

This was something that I thought about. I couldn't see any other test
in RISC-V doing disassembly tests for new instructions. I could have
missed something.

I guess this is due to the disassembler using the same opcode table (and
the same match function) as the assembly side.
With this, an AMOCAS.D/RV32 or AMOCAS.Q having odd registers in RD
and RS2 will disassemble into an '.insn'.

>
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/zacas-fail-32.d
> > @@ -0,0 +1,3 @@
> > +#as: -march=rv32ia_zacas
> > +#source: zacas-fail.s
> > +#error_output: zacas-fail-32.l
> > \ No newline at end of file
>
> Nit: You will want to address all instances of this.

Sure. As this is a RFC patch for an early spec, rather than something to
be committed, it doesn't call for a v3 as of yet, but I'll keep it in
mind and change it in the next patch to be sent.

Thank you again,
G.