[PATCH v6 02/15] RISC-V: Add support for the Zvbc extension

[Philipp Tomsich]

Same on the .vv:
>
> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & have Zvbc() & sizeof(xlen) == 64)
+ <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111    if
(haveRVV() & have Zvbc() & sizeof(xlen) == 64)


On Mon, 17 Jul 2023 at 09:26, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 17.07.2023 09:11, Philipp Tomsich wrote:
> > On Mon, 17 Jul 2023 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 01.07.2023 07:20, Christoph Muellner wrote:
> >>> --- a/opcodes/riscv-opc.c
> >>> +++ b/opcodes/riscv-opc.c
> >>> @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> >>>  {"vwsll.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> >>>  {"vwsll.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
> >>>
> >>> +/* Zvbc instructions.  */
> >>> +{"vclmul.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> >>> +{"vclmul.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
> >>
> >> I realize this is more a spec question than an implementation one, but
> >> implementation might be affected by the answer to the question: What
> >> exactly are this and ...
> >>
> >>> +{"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> >>> +{"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
> >>
> >> ... this insn doing in RV32 mode? There are no 64 bits to take from
> >> the GPR, yet that's what the doc presently says. Is the value coming
> >> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> >> RV64-only insn? (Note how the doc explicitly describes the behavior
> >> for vandn's scalar-source form; the only thing left to be implied
> >> there is that truncation / sign-extension are to - I assume - element
> >> size, but maybe that's said somewhere in more general terms.
> >
> >
> > According to the pull-request for the SAIL model (which will in the
> > future be auto-generated into the specification documents and often
> > clarifies on parts of the specification where the English text is
> > ambiguous or imprecise), these are defined for RV64 only:
> >>
> >> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> >> + <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111    if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> >
> > Consequently, these should only be allowed for RV64.
>
> Oh, even the .vv insn is RV64 only (I had asked about the .vx one)? Plus
> then why not sizeof(xlen) >= 64?
>
> Jan