[PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension
Christoph Muellner
christoph.muellner@vrull.eu
Sat Jul 1 05:20:55 GMT 2023
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvksed is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksed.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksed.d: New test.
* testsuite/gas/riscv/zvksed.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
(MASK_VSM4K_VI): New.
(MATCH_VSM4R_VS): New.
(MASK_VSM4R_VS): New.
(MATCH_VSM4R_VV): New.
(MASK_VSM4R_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksed.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksed instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvksed.s | 4 ++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
6 files changed, 38 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksed.d
create mode 100644 gas/testsuite/gas/riscv/zvksed.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 696b5c10147..f3f8a7401d9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1268,6 +1268,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2448,6 +2449,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
return (riscv_subset_supports (rps, "zvknha")
|| riscv_subset_supports (rps, "zvknhb"));
+ case INSN_CLASS_ZVKSED:
+ return riscv_subset_supports (rps, "zvksed");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2648,6 +2651,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvknha");
case INSN_CLASS_ZVKNHB:
return _("zvknhb");
+ case INSN_CLASS_ZVKSED:
+ return _("zvksed");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+8683a277[ ]+vsm4k.vi[ ]+v4,v8,7
+[ ]+[0-9a-f]+:[ ]+a2882277[ ]+vsm4r.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6882277[ ]+vsm4r.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@
+ vsm4k.vi v4, v8, 0
+ vsm4k.vi v4, v8, 7
+ vsm4r.vv v4, v8
+ vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 95c4188d084..39c0cadd686 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2198,6 +2198,13 @@
#define MASK_VSHA2CL_VV 0xfe00707f
#define MATCH_VSHA2MS_VV 0xb6002077
#define MASK_VSHA2MS_VV 0xfe00707f
+/* Zvksed instructions. */
+#define MATCH_VSM4K_VI 0x86002077
+#define MASK_VSM4K_VI 0xfe00707f
+#define MATCH_VSM4R_VS 0xa6082077
+#define MASK_VSM4R_VS 0xfe0ff07f
+#define MATCH_VSM4R_VV 0xa2082077
+#define MASK_VSM4R_VV 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3348,6 +3355,10 @@ DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
+/* Zvksed instructions. */
+DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
+DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
+DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 77207ea79b2..c378cce71c7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -421,6 +421,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKNHA,
INSN_CLASS_ZVKNHB,
INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+ INSN_CLASS_ZVKSED,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 297fda85af5..095af039040 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1930,6 +1930,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
+/* Zvksed instructions. */
+{"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VSM4K_VI, match_opcode, 0},
+{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
+{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
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