[PATCH v2] RISC-V: don't disassemble unrecognized insns as .byte

Nelson Chu nelson@rivosinc.com
Tue Jan 31 01:47:00 GMT 2023


Yeah, I think this is what we need and should be what most people
expect, so it looks good to me.

Thanks
Nelson

On Mon, Jan 30, 2023 at 10:40 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> Insn width granularity being 16 bits, producing byte granular output
> isn't very useful. With there being a way to specific otherwise
> unknown insns to the assembler, use that same representation (to be
> precise: its <length>,<encoding> flavor) for disassembly.
> ---
> v2: Switch to using .insn.
>
> --- a/binutils/testsuite/binutils-all/riscv/unknown.d
> +++ b/binutils/testsuite/binutils-all/riscv/unknown.d
> @@ -1,11 +1,11 @@
>  #as: -march=rv32ic
>  #objdump: -d
>  # Test the disassembly of unknown instruction encodings, specifically,
> -# ensure that we generate a .?byte opcode.
> +# ensure that we generate a .insn directive.
>
>  #...
>  Disassembly of section \.text:
>
>  [0-9a-f]+ <\.text>:
> -   [0-9a-f]+:  0052018b                \.4byte 0x52018b
> -   [0-9a-f]+:  9c45                    \.2byte 0x9c45
> +   [0-9a-f]+:  0052018b                \.insn  4, 0x0052018b
> +   [0-9a-f]+:  9c45                    \.insn  2, 0x9c45
> --- a/gas/testsuite/gas/riscv/insn.d
> +++ b/gas/testsuite/gas/riscv/insn.d
> @@ -92,25 +92,25 @@ Disassembly of section .text:
>  [^:]+:[        ]+607f 0000 0000 0000[  ]+[._a-z].*
>  [^:]+:[        ]+0000 0000 0000 0000 ?
>  [^:]+:[        ]+0000 0000 0000 ?
> -[^:]+:[        ]+007f 0000 0000 0000[  ]+\.byte[       ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
> +[^:]+:[        ]+007f 0000 0000 0000[  ]+\.insn[       ]+10, +0x8000000000000000007f
>  [^:]+:[        ]+8000 ?
> -[^:]+:[        ]+007f 0000 0000 0000[  ]+\.byte[       ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
> +[^:]+:[        ]+007f 0000 0000 0000[  ]+\.insn[       ]+10, +0x8000000000000000007f
>  [^:]+:[        ]+8000 ?
> -[^:]+:[        ]+607f 89ab 4567 0123[  ]+\.byte[       ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +[^:]+:[        ]+607f 89ab 4567 0123[  ]+\.insn[       ]+22, 0xfedcba98765432100123456789ab607f
>  [^:]+:[        ]+3210 7654 ba98 fedc ?
>  [^:]+:[        ]+0000 0000 0000 ?
> -[^:]+:[        ]+607f 89ab 4567 0123[  ]+\.byte[       ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +[^:]+:[        ]+607f 89ab 4567 0123[  ]+\.insn[       ]+22, 0xfedcba98765432100123456789ab607f
>  [^:]+:[        ]+3210 7654 ba98 fedc ?
>  [^:]+:[        ]+0000 0000 0000 ?
> -[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
> +[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.insn[       ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
>  [^:]+:[        ]+89ab 4567 0123 3210 ?
>  [^:]+:[        ]+7654 ba98 00dc ?
> -[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
> +[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.insn[       ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
>  [^:]+:[        ]+89ab 4567 0123 3210 ?
>  [^:]+:[        ]+7654 ba98 00dc ?
> -[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
> +[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.insn[       ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
>  [^:]+:[        ]+89ab 4567 0123 3210 ?
>  [^:]+:[        ]+7654 ba98 fedc ?
> -[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
> +[^:]+:[        ]+607f 33cc 55aa cdef[  ]+\.insn[       ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
>  [^:]+:[        ]+89ab 4567 0123 3210 ?
>  [^:]+:[        ]+7654 ba98 fedc ?
> --- a/gas/testsuite/gas/riscv/insn-na.d
> +++ b/gas/testsuite/gas/riscv/insn-na.d
> @@ -73,11 +73,11 @@ Disassembly of section .text:
>  [^:]+:[        ]+007f 0000 0000 0000 0000[     ]+[._a-z].*
>  [^:]+:[        ]+0000107f 00000000 00000000[   ]+[._a-z].*
>  [^:]+:[        ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[       ]+[._a-z].*
> -[^:]+:[        ]+007f 0000 0000 0000 8000[     ]+\.byte[       ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
> -[^:]+:[        ]+007f 0000 0000 0000 8000[     ]+\.byte[       ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
> -[^:]+:[        ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[       ]+\.byte[       ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> -[^:]+:[        ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[       ]+\.byte[       ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> -[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[       ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
> -[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[       ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
> -[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[       ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
> -[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[       ]+\.byte[       ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
> +[^:]+:[        ]+007f 0000 0000 0000 8000[     ]+\.insn[       ]+10, +0x8000000000000000007f
> +[^:]+:[        ]+007f 0000 0000 0000 8000[     ]+\.insn[       ]+10, +0x8000000000000000007f
> +[^:]+:[        ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[       ]+\.insn[       ]+22, 0xfedcba98765432100123456789ab607f
> +[^:]+:[        ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[       ]+\.insn[       ]+22, 0xfedcba98765432100123456789ab607f
> +[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[       ]+\.insn[       ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
> +[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[       ]+\.insn[       ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
> +[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[       ]+\.insn[       ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
> +[^:]+:[        ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[       ]+\.insn[       ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -650,7 +650,8 @@ riscv_disassemble_insn (bfd_vma memaddr,
>    static bool init = false;
>    static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
>    struct riscv_private_data *pd;
> -  int insnlen;
> +  int insnlen, i;
> +  bool printed;
>
>  #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
>
> @@ -666,8 +667,6 @@ riscv_disassemble_insn (bfd_vma memaddr,
>
>    if (info->private_data == NULL)
>      {
> -      int i;
> -
>        pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
>        pd->gp = 0;
>        pd->print_addr = 0;
> @@ -783,37 +782,28 @@ riscv_disassemble_insn (bfd_vma memaddr,
>         }
>      }
>
> -  /* We did not find a match, so just print the instruction bits.  */
> +  /* We did not find a match, so just print the instruction bits in
> +     the shape of an assembler .insn directive.  */
>    info->insn_type = dis_noninsn;
> -  switch (insnlen)
> +  (*info->fprintf_styled_func)
> +    (info->stream, dis_style_assembler_directive, ".insn");
> +  (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
> +  (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
> +                               "%d", insnlen);
> +  (*info->fprintf_styled_func) (info->stream, dis_style_text, ", ");
> +  (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x");
> +  for (i = insnlen, printed = false; i >= 2; )
>      {
> -    case 2:
> -    case 4:
> -    case 8:
> -      (*info->fprintf_styled_func)
> -       (info->stream, dis_style_assembler_directive, ".%dbyte", insnlen);
> -      (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
> +      i -= 2;
> +      word = bfd_get_bits (packet + i, 16, false);
> +      if (!word && !printed)
> +       continue;
> +
>        (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
> -                                   "0x%llx", (unsigned long long) word);
> -      break;
> -    default:
> -      {
> -        int i;
> -       (*info->fprintf_styled_func)
> -         (info->stream, dis_style_assembler_directive, ".byte");
> -       (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
> -        for (i = 0; i < insnlen; ++i)
> -          {
> -            if (i > 0)
> -             (*info->fprintf_styled_func) (info->stream, dis_style_text,
> -                                           ", ");
> -           (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
> -                                         "0x%02x",
> -                                         (unsigned int) (*packet++));
> -          }
> -      }
> -      break;
> +                                   "%04x", (unsigned int) word);
> +      printed = true;
>      }
> +
>    return insnlen;
>  }
>


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