[RFC PATCH v1] RISC-V: Support Zicond extension

[Jeff Law]

On 1/20/23 17:29, Philipp Tomsich wrote:
> *** Zicond is not FROZEN at this time. Do not merge until FROZEN. ***
> 
> This implements the Zicond (conditional integer operations) extension,
> as of version 1.0-draft-20230120.
> 
> The Zicond extension acts as a building block for branchless sequences
> including conditional-arithmetic, conditional-logic and
> conditional-select/move.
> The following instructions constitute Zicond:
>    - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
>    - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1
> 
> See
>    https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
> for the proposed specification and usage details.
> 
> bfd/ChangeLog:
> 
> 	* elfxx-riscv.c (riscv_multi_subset_supports): Recognize
>          INSN_CLASS_XVENTANACONDOPS.
> 	(riscv_multi_subset_supports_ext): Recognize
> 	INSN_CLASS_XVENTANACONDOPS,
> 
> gas/ChangeLog:
> 
> 	* testsuite/gas/riscv/zicond.d: New test.
> 	* testsuite/gas/riscv/zicond.s: New test.
> 
> include/ChangeLog:
> 
> 	* opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
> 	(MASK_CZERO_EQZ): Define.
> 	(MATCH_CZERO_NEZ): Define,
> 	(MASK_CZERO_NEZ): Define.
> 	(DECLARE_INSN): Add czero.eqz and czero.nez.
> 	* opcode/riscv.h (enum riscv_insn_class): Add
>          INSN_CLASS_ZICOND
> 
> opcodes/ChangeLog:
> 
> 	* riscv-opc.c: Add czero.eqz and czero.nez.
Given this extension is derived from the Ventana condops extension, I 
may be somewhat biased.  The mnemonics and encoding is obviously 
different, but the behavior is the same (perhaps differing in timing 
characteristics, but I think that's outside of what we care about here).

I assume nobody cares about gdbsim, so nothing to do there.  With that 
assumption this is fine to go forward once the spec freezes.

jeff