[PATCH 1/3] RISC-V: prefer SLT{,U} aliases for SLTI{,U}
Jan Beulich
jbeulich@suse.com
Fri Jan 13 10:19:19 GMT 2023
While not spelled out by the spec, gas has been supporting these aliases
virtually forever. Yet they were unused by the disassembler because of
sitting later in the table. Move the non-aliases down.
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -45,6 +45,9 @@ Disassembly of section .text:
[^:]+: R_RISCV_JAL[ ]+target
[^:]+:[ ]+fa5ff56f[ ]+jal[ ]+a0,0 \<target\>
[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+0015a513[ ]+slt[ ]+a0,a1,1
+[^:]+:[ ]+0015b513[ ]+seqz[ ]+a0,a1
+[^:]+:[ ]+0025b513[ ]+sltu[ ]+a0,a1,2
[^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
[^:]+:[ ]+0511[ ]+add[ ]+a0,a0,4 # .*
[^:]+:[ ]+002c[ ]+add[ ]+a1,sp,8
@@ -52,9 +55,9 @@ Disassembly of section .text:
[^:]+:[ ]+41a8[ ]+lw[ ]+a0,64\(a1\)
[^:]+:[ ]+c1a8[ ]+sw[ ]+a0,64\(a1\)
[^:]+:[ ]+8d6d[ ]+and[ ]+a0,a0,a1
-[^:]+:[ ]+d9c9[ ]+beqz[ ]+a1,0 \<target\>
+[^:]+:[ ]+d1d9[ ]+beqz[ ]+a1,0 \<target\>
[^:]+: R_RISCV_RVC_BRANCH[ ]+target
-[^:]+:[ ]+bf41[ ]+j[ ]+0 \<target\>
+[^:]+:[ ]+b751[ ]+j[ ]+0 \<target\>
[^:]+: R_RISCV_RVC_JUMP[ ]+target
[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -30,6 +30,10 @@ target:
.insn uj JAL, a0, target
.insn j JAL, a0, target
+ .insn i OP_IMM, 2, a0, a1, 1
+ .insn i OP_IMM, 3, a0, a1, 1
+ .insn i OP_IMM, 3, a0, a1, 2
+
.insn cr C2, 0x8, a0, a1
.insn ci C1, 0x0, a0, 4
.insn ciw C0, 0x0, a1, 1
--- a/gas/testsuite/gas/riscv/insn-dwarf.d
+++ b/gas/testsuite/gas/riscv/insn-dwarf.d
@@ -38,49 +38,52 @@ insn.s +29 +0x54.*
insn.s +30 +0x58.*
insn.s +31 +0x5c.*
insn.s +33 +0x60.*
-insn.s +34 +0x62.*
-insn.s +35 +0x64.*
-insn.s +36 +0x66.*
-insn.s +37 +0x68.*
-insn.s +38 +0x6a.*
-insn.s +39 +0x6c.*
-insn.s +40 +0x6e.*
-insn.s +41 +0x70.*
-insn.s +43 +0x72.*
-insn.s +44 +0x76.*
-insn.s +45 +0x7a.*
-insn.s +46 +0x7e.*
-insn.s +47 +0x82.*
-insn.s +48 +0x86.*
-insn.s +49 +0x8a.*
-insn.s +50 +0x8e.*
-insn.s +51 +0x92.*
-insn.s +52 +0x96.*
-insn.s +53 +0x9a.*
-insn.s +54 +0x9e.*
-insn.s +55 +0xa2.*
+insn.s +34 +0x64.*
+insn.s +35 +0x68.*
+insn.s +37 +0x6c.*
+insn.s +38 +0x6e.*
+insn.s +39 +0x70.*
+insn.s +40 +0x72.*
+insn.s +41 +0x74.*
+insn.s +42 +0x76.*
+insn.s +43 +0x78.*
+insn.s +44 +0x7a.*
+insn.s +45 +0x7c.*
+insn.s +47 +0x7e.*
+insn.s +48 +0x82.*
+insn.s +49 +0x86.*
+insn.s +50 +0x8a.*
+insn.s +51 +0x8e.*
+insn.s +52 +0x92.*
+insn.s +53 +0x96.*
+insn.s +54 +0x9a.*
+insn.s +55 +0x9e.*
+insn.s +56 +0xa2.*
insn.s +57 +0xa6.*
-insn.s +59 +0xaa.*
-insn.s +60 +0xac.*
-insn.s +61 +0xb0.*
-insn.s +62 +0xb6.*
-insn.s +63 +0xbe.*
-insn.s +64 +0xc8.*
-insn.s +65 +0xd4.*
-insn.s +66 +0xea.*
-insn.s +67 +0xec.*
-insn.s +68 +0xf0.*
-insn.s +69 +0xf6.*
-insn.s +70 +0xfe.*
-insn.s +71 +0x108.*
-insn.s +72 +0x114.*
-insn.s +74 +0x12a.*
-insn.s +75 +0x134.*
-insn.s +76 +0x13e.*
-insn.s +77 +0x154.*
-insn.s +78 +0x16a.*
-insn.s +79 +0x180.*
-insn.s +80 +0x196.*
-insn.s +81 +0x1ac.*
-insn.s +- +0x1c2
+insn.s +58 +0xaa.*
+insn.s +59 +0xae.*
+insn.s +61 +0xb2.*
+insn.s +63 +0xb6.*
+insn.s +64 +0xb8.*
+insn.s +65 +0xbc.*
+insn.s +66 +0xc2.*
+insn.s +67 +0xca.*
+insn.s +68 +0xd4.*
+insn.s +69 +0xe0.*
+insn.s +70 +0xf6.*
+insn.s +71 +0xf8.*
+insn.s +72 +0xfc.*
+insn.s +73 +0x102.*
+insn.s +74 +0x10a.*
+insn.s +75 +0x114.*
+insn.s +76 +0x120.*
+insn.s +78 +0x136.*
+insn.s +79 +0x140.*
+insn.s +80 +0x14a.*
+insn.s +81 +0x160.*
+insn.s +82 +0x176.*
+insn.s +83 +0x18c.*
+insn.s +84 +0x1a2.*
+insn.s +85 +0x1b8.*
+insn.s +- +0x1ce
#pass
--- a/gas/testsuite/gas/riscv/insn-na.d
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -36,6 +36,9 @@ Disassembly of section .text:
[^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
[^:]+:[ ]+fa9ff56f[ ]+jal[ ]+a0,0 \<target\>
[^:]+:[ ]+fa5ff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+:[ ]+0015a513[ ]+slti[ ]+a0,a1,1
+[^:]+:[ ]+0015b513[ ]+sltiu[ ]+a0,a1,1
+[^:]+:[ ]+0025b513[ ]+sltiu[ ]+a0,a1,2
[^:]+:[ ]+852e[ ]+c\.mv[ ]+a0,a1
[^:]+:[ ]+0511[ ]+c\.addi[ ]+a0,4 # .*
[^:]+:[ ]+002c[ ]+c\.addi4spn[ ]+a1,sp,8
@@ -43,8 +46,8 @@ Disassembly of section .text:
[^:]+:[ ]+41a8[ ]+c\.lw[ ]+a0,64\(a1\)
[^:]+:[ ]+c1a8[ ]+c\.sw[ ]+a0,64\(a1\)
[^:]+:[ ]+8d6d[ ]+c\.and[ ]+a0,a1
-[^:]+:[ ]+d9c9[ ]+c\.beqz[ ]+a1,0 \<target\>
-[^:]+:[ ]+bf41[ ]+c\.j[ ]+0 \<target\>
+[^:]+:[ ]+d1d9[ ]+c\.beqz[ ]+a1,0 \<target\>
+[^:]+:[ ]+b751[ ]+c\.j[ ]+0 \<target\>
[^:]+:[ ]+68c58543[ ]+fmadd\.s[ ]+fa0,fa1,fa2,fa3,rne
[^:]+:[ ]+68c58543[ ]+fmadd\.s[ ]+fa0,fa1,fa2,fa3,rne
[^:]+:[ ]+68c58543[ ]+fmadd\.s[ ]+fa0,fa1,fa2,fa3,rne
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -448,12 +448,12 @@ const struct riscv_opcode riscv_opcodes[
{"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
{"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT|MASK_RS2, match_opcode, INSN_ALIAS },
{"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT|MASK_RS1, match_opcode, INSN_ALIAS },
-{"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
{"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
{"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
-{"sltiu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
+{"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
{"sltu", 0, INSN_CLASS_I, "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
{"sltu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },
+{"sltiu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
{"sgt", 0, INSN_CLASS_I, "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS },
{"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
{"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE },
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