[RFC PATCH v3 7/8] RISC-V: Add Zvksh ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvksh ISA extension instructions, which are
part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c               |  5 +++++
 gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
 gas/testsuite/gas/riscv/zvksh.s |  3 +++
 include/opcode/riscv-opc.h      |  8 ++++++++
 include/opcode/riscv.h          |  1 +
 opcodes/riscv-opc.c             |  4 ++++
 6 files changed, 32 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2163117d451..f333c26189a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1215,6 +1215,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2380,6 +2381,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_ZVKSED:
       return riscv_subset_supports (rps, "zvksed");
+    case INSN_CLASS_ZVKSH:
+      return riscv_subset_supports (rps, "zvksh");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2550,6 +2553,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknhb");
     case INSN_CLASS_ZVKSED:
       return _("zvksed");
+    case INSN_CLASS_ZVKSH:
+      return _("zvksh");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae8fa277[ 	]+vsm3c.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+82862277[ 	]+vsm3me.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@
+	vsm3c.vi v4, v8, 0
+	vsm3c.vi v4, v8, 31
+	vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ae9a89b0bd2..c534fd095e0 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2126,6 +2126,11 @@
 #define MASK_VSM4RVV 0xfe0ff07f
 #define MATCH_VSM4RVS 0xa6082077
 #define MASK_VSM4RVS 0xfe0ff07f
+/* Zvksh instructions.  */
+#define MATCH_VSM3CVI 0xae002077
+#define MASK_VSM3CVI 0xfe00707f
+#define MATCH_VSM3MEVV 0x82002077
+#define MASK_VSM3MEVV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3227,6 +3232,9 @@ DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
 DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI)
 DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV)
 DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS)
+/* Zvksh instructions.  */
+DECLARE_INSN(vsm3cvi, MATCH_VSM3CVI, MASK_VSM3CVI)
+DECLARE_INSN(vsm3mevv, MATCH_VSM3MEVV, MASK_VSM3MEVV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1910ea7529c..5399a0bb991 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
+  INSN_CLASS_ZVKSH,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 98d17ef8b03..798ce56abeb 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1858,6 +1858,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0},
 {"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0},
 
+/* Zvksh instructions.  */
+{"vsm3c.vi",     0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3CVI, MASK_VSM3CVI, match_opcode, 0},
+{"vsm3me.vv",    0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3MEVV, MASK_VSM3MEVV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1