[RFC PATCH v3 3/8] RISC-V: Add Zvkned ISA extension support
Christoph Muellner
christoph.muellner@vrull.eu
Mon Feb 13 13:39:44 GMT 2023
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkned ISA extension instructions, which are
part of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v3:
- Rename Zvkns -> Zvkned
Changes in v2:
- Rename Zvkn -> Zvkns
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 13 ++++++++++++
6 files changed, 88 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkned.d
create mode 100644 gas/testsuite/gas/riscv/zvkned.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9e0dee9cc72..51ddaace420 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1207,6 +1207,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2361,6 +2362,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
return riscv_subset_supports (rps, "zvkg");
+ case INSN_CLASS_ZVKNED:
+ return riscv_subset_supports (rps, "zvkned");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2523,6 +2526,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkb");
case INSN_CLASS_ZVKG:
return _("zvkg");
+ case INSN_CLASS_ZVKNED:
+ return _("zvkned");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvkned.d
new file mode 100644
index 00000000000..0b09da9dbc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkned
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvkned.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.s
@@ -0,0 +1,13 @@
+ vaesdf.vv v4, v8
+ vaesdf.vs v4, v8
+ vaesdm.vv v4, v8
+ vaesdm.vs v4, v8
+ vaesef.vv v4, v8
+ vaesef.vs v4, v8
+ vaesem.vv v4, v8
+ vaesem.vs v4, v8
+ vaeskf1.vi v4, v8, 2
+ vaeskf1.vi v4, v8, 14
+ vaeskf2.vi v4, v8, 2
+ vaeskf2.vi v4, v8, 14
+ vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 03eda5a9e49..5f593222ea6 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2089,6 +2089,29 @@
#define MASK_VGHSHVV 0xfe00707f
#define MATCH_VGMULVV 0xa208a077
#define MASK_VGMULVV 0xfe0ff07f
+/* Zvkned instructions. */
+#define MATCH_VAESDFVV 0xa200a077
+#define MASK_VAESDFVV 0xfe0ff07f
+#define MATCH_VAESDFVS 0xa600a077
+#define MASK_VAESDFVS 0xfe0ff07f
+#define MATCH_VAESDMVV 0xa2002077
+#define MASK_VAESDMVV 0xfe0ff07f
+#define MATCH_VAESDMVS 0xa6002077
+#define MASK_VAESDMVS 0xfe0ff07f
+#define MATCH_VAESEFVV 0xa201a077
+#define MASK_VAESEFVV 0xfe0ff07f
+#define MATCH_VAESEFVS 0xa601a077
+#define MASK_VAESEFVS 0xfe0ff07f
+#define MATCH_VAESEMVV 0xa2012077
+#define MASK_VAESEMVV 0xfe0ff07f
+#define MATCH_VAESEMVS 0xa6012077
+#define MASK_VAESEMVS 0xfe0ff07f
+#define MATCH_VAESKF1VI 0x8a002077
+#define MASK_VAESKF1VI 0xfe00707f
+#define MATCH_VAESKF2VI 0xaa002077
+#define MASK_VAESKF2VI 0xfe00707f
+#define MATCH_VAESZVS 0xa603a077
+#define MASK_VAESZVS 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3170,6 +3193,18 @@ DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
/* Zvkg instructions. */
DECLARE_INSN(vghshvv, MATCH_VGHASHVV, MASK_VGHASHVV)
DECLARE_INSN(vgmulvv, MATCH_VGMULTVV, MASK_VGMULTVV)
+/* Zvkned instructions. */
+DECLARE_INSN(vaesdfvv, MATCH_VAESDFVV, MASK_VAESDFVV)
+DECLARE_INSN(vaesdfvs, MATCH_VAESDFVS, MASK_VAESDFVS)
+DECLARE_INSN(vaesdmvv, MATCH_VAESDMVV, MASK_VAESDMVV)
+DECLARE_INSN(vaesdmvs, MATCH_VAESDMVS, MASK_VAESDMVS)
+DECLARE_INSN(vaesefvv, MATCH_VAESEFVV, MASK_VAESEFVV)
+DECLARE_INSN(vaesefvs, MATCH_VAESEFVS, MASK_VAESEFVS)
+DECLARE_INSN(vaesemvv, MATCH_VAESEMVV, MASK_VAESEMVV)
+DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
+DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
+DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
+DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 9e883f030d6..4b7e72150e5 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
+ INSN_CLASS_ZVKNED,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0bb0bb4cce7..3465670d951 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1835,6 +1835,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSHVV, MASK_VGHSHVV, match_opcode, 0},
{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMULVV, MASK_VGMULVV, match_opcode, 0},
+/* Zvkned instructions. */
+{"vaesdf.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDFVV, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdf.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDFVS, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdm.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDMVV, MASK_VAESDMVV, match_opcode, 0},
+{"vaesdm.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDMVS, MASK_VAESDMVV, match_opcode, 0},
+{"vaesef.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEFVV, MASK_VAESEFVV, match_opcode, 0},
+{"vaesef.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEFVS, MASK_VAESEFVV, match_opcode, 0},
+{"vaesem.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEMVV, MASK_VAESEMVV, match_opcode, 0},
+{"vaesem.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEMVS, MASK_VAESEMVV, match_opcode, 0},
+{"vaeskf1.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1VI, MASK_VAESKF1VI, match_opcode, 0},
+{"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
+{"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.39.1
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