[PATCH v2] x86: Remove the restriction for size of the mask register in AVX10

Jiang, Haochen haochen.jiang@intel.com
Tue Dec 19 05:15:10 GMT 2023


> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -823,6 +823,11 @@ static unsigned int sse2avx;  static unsigned int
> > use_unaligned_vector_move;
> >
> >  /* Maximum permitted vector size. */
> > +static enum {
> > +    VSZ128 = 0,
> > +    VSZ256,
> > +    VSZ512,
> > +} Vsz;
> 
> Looks like this static variable is unused?
> 
> >  #define VSZ_DEFAULT VSZ512
> >  static unsigned int vector_size = VSZ_DEFAULT;
> 
> And this variable would then better be of the new enum type? Albeit ...
> 
> > @@ -6967,12 +6972,10 @@ VEX_check_encoding (const insn_template *t)
> >
> >    /* Vector size restrictions.  */
> >    if ((vector_size < VSZ512
> > -       && (t->opcode_modifier.evex == EVEX512
> > -	   || t->opcode_modifier.vsz >= VSZ512))
> > +       && t->opcode_modifier.evex == EVEX512)
> >        || (vector_size < VSZ256
> >  	  && (t->opcode_modifier.evex == EVEX256
> > -	      || t->opcode_modifier.vex == VEX256
> > -	      || t->opcode_modifier.vsz >= VSZ256)))
> > +	      || t->opcode_modifier.vex == VEX256)))
> >      {
> 
> ... the use of < here makes me wonder whether an enum is really the best
> thing to use. Maybe better to stick to #define-s?

Maybe since the define-s are more straightforward than enum. I am going to
change that.

Thx,
Haochen

> 
> Jan


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