[PATCH v2] RISC-V: emit R_RISCV_RELAX for the la pseudo instruction

[Andreas Schwab]

On Sep 20 2023, Rui Ueyama via Binutils wrote:

> @@ -4049,6 +4057,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
>        break;
>  
>      case BFD_RELOC_RISCV_GOT_HI20:
> +      /* R_RISCV_GOT_HI20 and the following R_RISCV_LO12_I are relaxable
> +	 only if it is created as a result of la or lga assembler macros. */
> +      if (fixP->tc_fix_data.source_macro == M_LA ||
> +	  fixP->tc_fix_data.source_macro == M_LGA)

Line break before the operator, not after.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
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