[RISCV] [GNU AS] Possible `vmsge{u}.vx` instruction lowering bug?

[Jan Beulich]

On 29.08.2023 08:52, im Kiva via Binutils wrote:
> Hi maintainers,
> 
> I discovered that GNU Assembler (as) lowers `vmsge.vx` and `vmsgeu.vx` (pseudo
> instructions from RISC-V Vector Extension [1]) when the destination
> register is v0 as follows:
> 
> vmsge{u}.vx v0, v4, a0, v0.t, v2
> 
> will be expanded to:
> 
> vmslt{u}.vx v2, v4, a0, v0.t
> vmandn.mm v0, v0, v2
> 
> You can inspect the lowering result with Godbolt [2].
> However, according to the Vector specification [1] page 52. The "desugared"
> `vmslt{u}.vx` is not masked:
> 
>> masked va >= x, vd == v0
>>   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
>>   expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
> 
> So the spec-expected result of the example above should be:
> vmslt{u}.vx v2, v4, a0 <-- no v0.t here
> vmandn.mm v0, v0, v2
> 
> I thus submitted a patch to the LLVM [3], and it was accepted recently.
> 
> I am wondering if binutils considers it a bug, or if it is just intentional
> because of some historical and compatibility reasons.

I think this wants fixing alike in binutils: From looking at vector_macro(),
it appears that emitting the masked form is merely an accident resulting
from the inverted encoding of "masking". In particular, if masking was
indeed meant, I expect code there would be

		  if (vd == vm)
		    {
		      macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, vm);
		      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
		    }
		  else
		    ...

much like it is a few lines down from there. (Apparently the "else" path
omitted above is similarly affected.)

Jan