[PATCH] RISC-V: Fix opcode entries of "vmsge{,u}.vx"

[Nelson Chu]

Okay, in general INSN_MACRO should use match_never rather than match_opcode
and others, so looks correct and good to me.

Thanks
Nelson

On Sun, Aug 6, 2023 at 9:53 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Their check_func should be "match_never", not "match_opcode".  The reasons
> this error did not cause any disassembler errors are:
>
> 1.  The problem will not reproduce if "no-aliases" is specified
>     (because macro instructions are handled as aliases).
> 2.  If not, all affected compressed instructions or their aliases
>     precede before "vmsge{,u}.vx" macro instructions.
>
> However, it'll easily break if we reorder opcode entries.  This commit
> fixes this issue before the *accident* occurs.
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c (riscv_opcodes): Make sure that we never match to
>         vmsge{,u}.vx instructions unless specified in the assembler.
> ---
>  opcodes/riscv-opc.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 6a854736fec0..37c7694999ad 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1606,10 +1606,10 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSEQVV,
> MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS },
>  {"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTUVI,
> MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
>
> -{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE,
> match_opcode, INSN_MACRO },
> -{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE,
> match_opcode, INSN_MACRO },
> -{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU,
> match_opcode, INSN_MACRO },
> -{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU,
> match_opcode, INSN_MACRO },
> +{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE,
> match_never, INSN_MACRO },
> +{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE,
> match_never, INSN_MACRO },
> +{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU,
> match_never, INSN_MACRO },
> +{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU,
> match_never, INSN_MACRO },
>
>  {"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV,
> MASK_VMINUVV, match_opcode, 0},
>  {"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX,
> MASK_VMINUVX, match_opcode, 0},
>
> base-commit: 5e66f55c62e306afbcc93856bf06e542ddd00997
> --
> 2.41.0
>
>