[PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.

[Nelson Chu]

Committed, thanks.

Nelson

On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:

> Let --no-relax-gp only disable the gp relaxation for lui and pcrel
> relaxations, since x0 base and gp relaxations are different optimizations
> in fact, but just use the same function to handle.
>
> bfd/
>         * elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
>         set gp to zero when --no-relax-gp, then we should still keep the
>         x0 base relaxation.
>         (_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
>         --no-relax-gp, we will disable the gp relaxation in the
>         _bfd_riscv_relax_pc.
> ---
>  bfd/elfnn-riscv.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 499f51ee857..77a732b6a08 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
>                      bool undefined_weak)
>  {
>    struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> (link_info);
> -  bfd_vma gp = riscv_global_pointer_value (link_info);
> +  bfd_vma gp = htab->params->relax_gp
> +              ? riscv_global_pointer_value (link_info)
> +              : 0;
>
>    BFD_ASSERT (rel->r_offset + 4 <= sec->size);
>
> @@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
>                    || type == R_RISCV_TPREL_LO12_I
>                    || type == R_RISCV_TPREL_LO12_S)
>             relax_func = _bfd_riscv_relax_tls_le;
> -         else if (!bfd_link_pic (info) && htab->params->relax_gp
> +         else if (!bfd_link_pic (info)
>                    && (type == R_RISCV_PCREL_HI20
>                        || type == R_RISCV_PCREL_LO12_I
>                        || type == R_RISCV_PCREL_LO12_S))
> --
> 2.39.2 (Apple Git-143)
>
>