[PATCH 00/31] aarch64: Add SME2 support

[Jan Beulich]

On 30.03.2023 12:26, Richard Sandiford via Binutils wrote:
> Richard Sandiford (31):
>   aarch64: Add +sme2
>   aarch64: Add a _10 suffix to FLD_imm3
>   aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array
>   aarch64: Add support for vgx2 and vgx4
>   aarch64; Add support for vector offset ranges
>   aarch64: Add support for predicate-as-counter registers
>   aarch64: Add the SME2 MOVA instructions
>   aarch64: Add the SME2 multivector LD1 and ST1 instructions

Less than a 3rd of the patches in this series have made it to my mailbox
(and the list archives), so commenting on e.g. the one above is difficult.
Nevertheless - according to the documentation LD1x (scalar plus immediate,
consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts
are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks
as if the use of SME2_INSN() there is wrong, unless the documentation is
categorizing these incorrectly).

Jan