[REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'Zihintntl' extension
Tsukasa OI
research_trasio@irq.a4lg.com
Sun Sep 18 10:13:22 GMT 2022
[DO NOT MERGE]
Until 'Zihintntl' extension is ratified and final version number is
determined, this patch should not merged upstream. This commit uses
unratified version 0.2 as in documentation (instead of possible 1.0
after ratification).
This commit adds 'Zihintntl' extension and its hint instructions.
This is based on:
<https://github.com/riscv/riscv-isa-manual/commit/c0db46f72a1cc409194bf7f11c09e69a387f16a0>
(latest commit of the 'master' branch as of this writing)
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl'
standard hint 'Z' extension. (riscv_multi_subset_supports): Add
handling for new instruction classes.
gas/ChangeLog:
* testsuite/gas/riscv/zihintntl.s: New test for 4-byte hint
instructions.
* testsuite/gas/riscv/zihintntl.d: Likewise.
* testsuite/gas/riscv/zihintntl-auto-c.d: Likewise but test auto
compression to 2-byte instructions.
* testsuite/gas/riscv/zihintntl-c.s: New test for 2-byte hint
instructions.
* testsuite/gas/riscv/zihintntl-c.d: Likewise.
* testsuite/gas/riscv/zihintntl-c-noalias.d: Likewise but
different output with -Mno-aliases.
* testsuite/gas/riscv/zihintntl-base.s: New test for base
instructions corresponding non-temporal locality hints.
* testsuite/gas/riscv/zihintntl-base.d: Likewise.
* testsuite/gas/riscv/zihintntl-base-noarch.d: Likewise but
without 'Zihintntl' extension in -march.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C.
(MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL,
MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL,
MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL,
MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL,
MATCH_C_NTL_ALL): New macros.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add non-temporal locality hint
instructions and aliases.
---
bfd/elfxx-riscv.c | 16 ++++++++++++
gas/testsuite/gas/riscv/zihintntl-auto-c.d | 17 ++++++++++++
.../gas/riscv/zihintntl-base-noarch.d | 25 ++++++++++++++++++
gas/testsuite/gas/riscv/zihintntl-base.d | 25 ++++++++++++++++++
gas/testsuite/gas/riscv/zihintntl-base.s | 17 ++++++++++++
gas/testsuite/gas/riscv/zihintntl-c-noalias.d | 17 ++++++++++++
gas/testsuite/gas/riscv/zihintntl-c.d | 17 ++++++++++++
gas/testsuite/gas/riscv/zihintntl-c.s | 9 +++++++
gas/testsuite/gas/riscv/zihintntl.d | 17 ++++++++++++
gas/testsuite/gas/riscv/zihintntl.s | 9 +++++++
include/opcode/riscv-opc.h | 26 +++++++++++++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 12 +++++++++
13 files changed, 209 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zihintntl-auto-c.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl-base-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl-base.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl-base.s
create mode 100644 gas/testsuite/gas/riscv/zihintntl-c-noalias.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl-c.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl-c.s
create mode 100644 gas/testsuite/gas/riscv/zihintntl.d
create mode 100644 gas/testsuite/gas/riscv/zihintntl.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e03b312a381..b37d89e769c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1160,6 +1160,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
+ {"zihintntl", ISA_SPEC_CLASS_DRAFT, 0, 2, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2285,6 +2286,11 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
return riscv_subset_supports (rps, "zifencei");
+ case INSN_CLASS_ZIHINTNTL:
+ return riscv_subset_supports (rps, "zihintntl");
+ case INSN_CLASS_ZIHINTNTL_AND_C:
+ return (riscv_subset_supports (rps, "zihintntl")
+ && riscv_subset_supports (rps, "c"));
case INSN_CLASS_ZIHINTPAUSE:
return riscv_subset_supports (rps, "zihintpause");
case INSN_CLASS_M:
@@ -2402,6 +2408,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zicsr";
case INSN_CLASS_ZIFENCEI:
return "zifencei";
+ case INSN_CLASS_ZIHINTNTL:
+ return "zihintntl";
+ case INSN_CLASS_ZIHINTNTL_AND_C:
+ if (!riscv_subset_supports (rps, "zihintntl")
+ && !riscv_subset_supports (rps, "c"))
+ return _ ("zihintntl' and `c");
+ else if (!riscv_subset_supports (rps, "zihintntl"))
+ return "zihintntl";
+ else
+ return "c";
case INSN_CLASS_ZIHINTPAUSE:
return "zihintpause";
case INSN_CLASS_M:
diff --git a/gas/testsuite/gas/riscv/zihintntl-auto-c.d b/gas/testsuite/gas/riscv/zihintntl-auto-c.d
new file mode 100644
index 00000000000..1e849d685e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-auto-c.d
@@ -0,0 +1,17 @@
+#as: -march=rv64ic_zihintntl
+#source: zihintntl.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+900a[ ]+ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
+[ ]+[0-9a-f]+:[ ]+900e[ ]+ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
+[ ]+[0-9a-f]+:[ ]+9012[ ]+ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
+[ ]+[0-9a-f]+:[ ]+9016[ ]+ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl-base-noarch.d b/gas/testsuite/gas/riscv/zihintntl-base-noarch.d
new file mode 100644
index 00000000000..5d3111cc3ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-base-noarch.d
@@ -0,0 +1,25 @@
+#as: -march=rv64ic
+#source: zihintntl-base.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00200033[ ]+add[ ]+zero,zero,sp
+[ ]+[0-9a-f]+:[ ]+01b28823[ ]+sb[ ]+s11,16\(t0\)
+[ ]+[0-9a-f]+:[ ]+00300033[ ]+add[ ]+zero,zero,gp
+[ ]+[0-9a-f]+:[ ]+01b28923[ ]+sb[ ]+s11,18\(t0\)
+[ ]+[0-9a-f]+:[ ]+00400033[ ]+add[ ]+zero,zero,tp
+[ ]+[0-9a-f]+:[ ]+01b28a23[ ]+sb[ ]+s11,20\(t0\)
+[ ]+[0-9a-f]+:[ ]+00500033[ ]+add[ ]+zero,zero,t0
+[ ]+[0-9a-f]+:[ ]+01b28b23[ ]+sb[ ]+s11,22\(t0\)
+[ ]+[0-9a-f]+:[ ]+900a[ ]+c\.add[ ]+zero,sp
+[ ]+[0-9a-f]+:[ ]+01b28c23[ ]+sb[ ]+s11,24\(t0\)
+[ ]+[0-9a-f]+:[ ]+900e[ ]+c\.add[ ]+zero,gp
+[ ]+[0-9a-f]+:[ ]+01b28d23[ ]+sb[ ]+s11,26\(t0\)
+[ ]+[0-9a-f]+:[ ]+9012[ ]+c\.add[ ]+zero,tp
+[ ]+[0-9a-f]+:[ ]+01b28e23[ ]+sb[ ]+s11,28\(t0\)
+[ ]+[0-9a-f]+:[ ]+9016[ ]+c\.add[ ]+zero,t0
+[ ]+[0-9a-f]+:[ ]+01b28f23[ ]+sb[ ]+s11,30\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl-base.d b/gas/testsuite/gas/riscv/zihintntl-base.d
new file mode 100644
index 00000000000..ae98de5b3d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-base.d
@@ -0,0 +1,25 @@
+#as: -march=rv64ic_zihintntl
+#source: zihintntl-base.s
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00200033[ ]+ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28823[ ]+sb[ ]+s11,16\(t0\)
+[ ]+[0-9a-f]+:[ ]+00300033[ ]+ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28923[ ]+sb[ ]+s11,18\(t0\)
+[ ]+[0-9a-f]+:[ ]+00400033[ ]+ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28a23[ ]+sb[ ]+s11,20\(t0\)
+[ ]+[0-9a-f]+:[ ]+00500033[ ]+ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28b23[ ]+sb[ ]+s11,22\(t0\)
+[ ]+[0-9a-f]+:[ ]+900a[ ]+c\.ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28c23[ ]+sb[ ]+s11,24\(t0\)
+[ ]+[0-9a-f]+:[ ]+900e[ ]+c\.ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28d23[ ]+sb[ ]+s11,26\(t0\)
+[ ]+[0-9a-f]+:[ ]+9012[ ]+c\.ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28e23[ ]+sb[ ]+s11,28\(t0\)
+[ ]+[0-9a-f]+:[ ]+9016[ ]+c\.ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28f23[ ]+sb[ ]+s11,30\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl-base.s b/gas/testsuite/gas/riscv/zihintntl-base.s
new file mode 100644
index 00000000000..6678fc9c2b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-base.s
@@ -0,0 +1,17 @@
+target:
+ add x0, x0, x2 # ntl.p1
+ sb s11, 2*0x8(t0)
+ add x0, x0, x3 # ntl.pall
+ sb s11, 2*0x9(t0)
+ add x0, x0, x4 # ntl.s1
+ sb s11, 2*0xa(t0)
+ add x0, x0, x5 # ntl.all
+ sb s11, 2*0xb(t0)
+ c.add x0, x2 # c.ntl.p1
+ sb s11, 2*0xc(t0)
+ c.add x0, x3 # c.ntl.pall
+ sb s11, 2*0xd(t0)
+ c.add x0, x4 # c.ntl.s1
+ sb s11, 2*0xe(t0)
+ c.add x0, x5 # c.ntl.all
+ sb s11, 2*0xf(t0)
diff --git a/gas/testsuite/gas/riscv/zihintntl-c-noalias.d b/gas/testsuite/gas/riscv/zihintntl-c-noalias.d
new file mode 100644
index 00000000000..cd4897a1eef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-c-noalias.d
@@ -0,0 +1,17 @@
+#as: -march=rv64ic_zihintntl
+#source: zihintntl-c.s
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+900a[ ]+c\.ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28423[ ]+sb[ ]+s11,8\(t0\)
+[ ]+[0-9a-f]+:[ ]+900e[ ]+c\.ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28523[ ]+sb[ ]+s11,10\(t0\)
+[ ]+[0-9a-f]+:[ ]+9012[ ]+c\.ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28623[ ]+sb[ ]+s11,12\(t0\)
+[ ]+[0-9a-f]+:[ ]+9016[ ]+c\.ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28723[ ]+sb[ ]+s11,14\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl-c.d b/gas/testsuite/gas/riscv/zihintntl-c.d
new file mode 100644
index 00000000000..0e71029d5ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-c.d
@@ -0,0 +1,17 @@
+#as: -march=rv64ic_zihintntl
+#source: zihintntl-c.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+900a[ ]+ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28423[ ]+sb[ ]+s11,8\(t0\)
+[ ]+[0-9a-f]+:[ ]+900e[ ]+ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28523[ ]+sb[ ]+s11,10\(t0\)
+[ ]+[0-9a-f]+:[ ]+9012[ ]+ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28623[ ]+sb[ ]+s11,12\(t0\)
+[ ]+[0-9a-f]+:[ ]+9016[ ]+ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28723[ ]+sb[ ]+s11,14\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl-c.s b/gas/testsuite/gas/riscv/zihintntl-c.s
new file mode 100644
index 00000000000..3f140d4f31b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl-c.s
@@ -0,0 +1,9 @@
+target:
+ c.ntl.p1
+ sb s11, 2*0x4(t0)
+ c.ntl.pall
+ sb s11, 2*0x5(t0)
+ c.ntl.s1
+ sb s11, 2*0x6(t0)
+ c.ntl.all
+ sb s11, 2*0x7(t0)
diff --git a/gas/testsuite/gas/riscv/zihintntl.d b/gas/testsuite/gas/riscv/zihintntl.d
new file mode 100644
index 00000000000..e7ff6fc322a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl.d
@@ -0,0 +1,17 @@
+#as: -march=rv64i_zihintntl
+#source: zihintntl.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00200033[ ]+ntl\.p1
+[ ]+[0-9a-f]+:[ ]+01b28023[ ]+sb[ ]+s11,0\(t0\)
+[ ]+[0-9a-f]+:[ ]+00300033[ ]+ntl\.pall
+[ ]+[0-9a-f]+:[ ]+01b28123[ ]+sb[ ]+s11,2\(t0\)
+[ ]+[0-9a-f]+:[ ]+00400033[ ]+ntl\.s1
+[ ]+[0-9a-f]+:[ ]+01b28223[ ]+sb[ ]+s11,4\(t0\)
+[ ]+[0-9a-f]+:[ ]+00500033[ ]+ntl\.all
+[ ]+[0-9a-f]+:[ ]+01b28323[ ]+sb[ ]+s11,6\(t0\)
diff --git a/gas/testsuite/gas/riscv/zihintntl.s b/gas/testsuite/gas/riscv/zihintntl.s
new file mode 100644
index 00000000000..0e7660ea361
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zihintntl.s
@@ -0,0 +1,9 @@
+target:
+ ntl.p1
+ sb s11, 2*0x0(t0)
+ ntl.pall
+ sb s11, 2*0x1(t0)
+ ntl.s1
+ sb s11, 2*0x2(t0)
+ ntl.all
+ sb s11, 2*0x3(t0)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 88b8d7ff595..2c33680a2b2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,23 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zihintntl hint instructions. */
+#define MATCH_NTL_P1 0x200033
+#define MASK_NTL_P1 0xffffffff
+#define MATCH_NTL_PALL 0x300033
+#define MASK_NTL_PALL 0xffffffff
+#define MATCH_NTL_S1 0x400033
+#define MASK_NTL_S1 0xffffffff
+#define MATCH_NTL_ALL 0x500033
+#define MASK_NTL_ALL 0xffffffff
+#define MATCH_C_NTL_P1 0x900a
+#define MASK_C_NTL_P1 0xffff
+#define MATCH_C_NTL_PALL 0x900e
+#define MASK_C_NTL_PALL 0xffff
+#define MATCH_C_NTL_S1 0x9012
+#define MASK_C_NTL_S1 0xffff
+#define MATCH_C_NTL_ALL 0x9016
+#define MASK_C_NTL_ALL 0xffff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
@@ -2852,6 +2869,15 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Zihintntl hint instructions. */
+DECLARE_INSN(ntl_p1, MATCH_NTL_P1, MASK_NTL_P1);
+DECLARE_INSN(ntl_pall, MATCH_NTL_PALL, MASK_NTL_PALL);
+DECLARE_INSN(ntl_s1, MATCH_NTL_S1, MASK_NTL_S1);
+DECLARE_INSN(ntl_all, MATCH_NTL_ALL, MASK_NTL_ALL);
+DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1);
+DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL);
+DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1);
+DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL);
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Unprivileged Counter/Timers CSRs. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index f1dabeaab8e..4b05ec7df41 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -366,6 +366,8 @@ enum riscv_insn_class
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
+ INSN_CLASS_ZIHINTNTL,
+ INSN_CLASS_ZIHINTNTL_AND_C,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZMMUL,
INSN_CLASS_F_OR_ZFINX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 79be78eb367..9ddf4a6de6d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -344,6 +344,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
{"addi", 0, INSN_CLASS_C, "d,CV,z", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
{"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
+{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, INSN_ALIAS },
+{"ntl.p1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_P1, MASK_NTL_P1, match_opcode, 0 },
+{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, INSN_ALIAS },
+{"ntl.pall", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_PALL, MASK_NTL_PALL, match_opcode, 0 },
+{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, INSN_ALIAS },
+{"ntl.s1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_S1, MASK_NTL_S1, match_opcode, 0 },
+{"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, INSN_ALIAS },
+{"ntl.all", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_ALL, MASK_NTL_ALL, match_opcode, 0 },
{"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
{"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
@@ -855,6 +863,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.addi4spn", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 },
{"c.addi16sp", 0, INSN_CLASS_C, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 },
{"c.addi", 0, INSN_CLASS_C, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
+{"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, 0 },
+{"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, 0 },
+{"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 },
+{"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 },
{"c.add", 0, INSN_CLASS_C, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 },
{"c.sub", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
{"c.and", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
--
2.34.1
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