[PATCH 3/3] RISC-V: add alias for SLLI.UW

[Jan Beulich]

Like e.g. SLLI's SLL alias, this insn would - for consistency - better
also have a SLL.UW alias, even if the spec doesn't mandate one (yet).

--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -45,7 +45,7 @@ Disassembly of section .text:
 [ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
 [ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
 [ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
-[ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+0825951b[ 	]+sll\.uw[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclr[ 	]+a0,a1,0x0
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bset[ 	]+a0,a1,0x0
@@ -62,6 +62,7 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0835951b[ 	]+sll\.uw[ 	]+a0,a1,0x3
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -54,6 +54,7 @@ target:
 	binv    a0, a1, a2
 	bext    a0, a1, a2
 	#aliases
+	sll.uw	a0, a1, 3
 	bclr    a0, a1, 31
 	bset    a0, a1, 31
 	binv    a0, a1, 31
--- a/gas/testsuite/gas/riscv/b-ext-64-na.d
+++ b/gas/testsuite/gas/riscv/b-ext-64-na.d
@@ -62,6 +62,7 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0835951b[ 	]+slli\.uw[ 	]+a0,a1,0x3
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -971,6 +971,7 @@ const struct riscv_opcode riscv_opcodes[
 {"zext.w",    64, INSN_CLASS_ZBA,  "d,s",   MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
 {"zext.w",    64, INSN_CLASS_I, "d,s",       0, (int) M_ZEXTW, match_never, INSN_MACRO },
 {"add.uw",    64, INSN_CLASS_ZBA,  "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
+{"sll.uw",    64, INSN_CLASS_ZBA,  "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, INSN_ALIAS },
 {"slli.uw",   64, INSN_CLASS_ZBA,  "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
 
 /* Zbc or zbkc instructions.  */