[PATCH 0/1] RISC-V: Fix CSR accessibility on vectors

[Tsukasa OI]

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_on_vector>

Previous:
<https://sourceware.org/pipermail/binutils/2022-September/122761.html>

This is a subset of previous CSR accessibility and implication patchset.
It seems making requirement of CSR_CLASS_V from 'V' to 'Zve32x' is less
debatable, I splitted this part as a separate patchset.

(Not strictly a subset; I added CSR accessibility test for 'V')

An excerpt (slightly modified) from previous cover letter follows:



On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they
require the 'V' extension.  However, there are a few vector subextensions
that implement vector subsets (intended for embedded processors).

-   'Zve64d' (superset of 'Zve64f')
-   'Zve64f' (superset of 'Zve32f' and 'Zve64x')
-   'Zve64x' (superset of 'Zve32x')
-   'Zve32f' (superset of 'Zve32x')
-   'Zve32x'

| Graph: Dependency graph of some vector/FP extensions and Zicsr
|
| +-------> D ---+----> F -----> Zicsr
| |         ^    |      ^
| |         |    /      |
| V ---> Zve64d ---> Zve64f ---> Zve64x
|                \      |           |
|                |      V           V
|                +-- Zve32f ---> Zve32x
|                                   |
|                                   |
|                                   +---> (Zicsr [should be added?])

They also require general purpose vector CSRs (vstart, vl, vtype and vlenb).
So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate
(they should require 'Zve32x' instead, the minimum vector subset).

Remaining CSRs are:

-   vxsat
-   vxrm
-   vcsr

They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions
for Embedded Processors" says:

> All Zve* extensions support all vector fixed-point arithmetic instructions
> (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and
> vsmul.vx are not supported for EEW=64 in Zve64*.

So, their minimum requirement shall be also 'Zve32x', not 'V'.

As a consequence, we can conclude that changing requirements of CSR_CLASS_V
from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings.

I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets
difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x'
with some exceptions).




Tsukasa OI (1):
  RISC-V: Fix vector CSR requirements

 gas/config/tc-riscv.c                        |  2 +-
 gas/testsuite/gas/riscv/csr-version-1p10.l   | 28 ++++++++++----------
 gas/testsuite/gas/riscv/csr-version-1p11.l   | 28 ++++++++++----------
 gas/testsuite/gas/riscv/csr-version-1p12.l   | 28 ++++++++++----------
 gas/testsuite/gas/riscv/csr-version-1p9p1.l  | 28 ++++++++++----------
 gas/testsuite/gas/riscv/vector-csrs-v.d      | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++
 gas/testsuite/gas/riscv/vector-csrs.s        | 12 +++++++++
 12 files changed, 195 insertions(+), 57 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d
 create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s


base-commit: f42546b6cc7468ac7d929181ed7b965ab60958ac
-- 
2.34.1